Lines Matching +full:risc +full:- +full:v

1 /* SPDX-License-Identifier: Apache-2.0 OR BSD-2-Clause */
3 // This file is dual-licensed, meaning that you can use it under your
40 // The generated code of this file depends on the following RISC-V extensions:
41 // - RV64I
42 // - RISC-V Vector ('V') with VLEN >= 128
43 // - RISC-V Vector SHA-2 Secure Hash extension ('Zvknha' or 'Zvknhb')
44 // - RISC-V Vector Cryptography Bit-manipulation extension ('Zvkb')
85 // Do 4 rounds of SHA-256.  w0 contains the current 4 message schedule words.
88 // computes 4 more message schedule words.  w1-w3 contain the next 3 groups of 4
113 	// Load the round constants into K0-K15.
116 	vle32.v		K0, (t0)
118 	vle32.v		K1, (t0)
120 	vle32.v		K2, (t0)
122 	vle32.v		K3, (t0)
124 	vle32.v		K4, (t0)
126 	vle32.v		K5, (t0)
128 	vle32.v		K6, (t0)
130 	vle32.v		K7, (t0)
132 	vle32.v		K8, (t0)
134 	vle32.v		K9, (t0)
136 	vle32.v		K10, (t0)
138 	vle32.v		K11, (t0)
140 	vle32.v		K12, (t0)
142 	vle32.v		K13, (t0)
144 	vle32.v		K14, (t0)
146 	vle32.v		K15, (t0)
149 	// message scheduling.  There are 4 words, so an 8-bit mask suffices.
151 	vmv.v.i		MASK, 0x01
155 	// is e8mf4.  We use index-load with the i8 indices {20, 16, 4, 0},
156 	// loaded using the 32-bit little endian value 0x00041014.
159 	vmv.v.x		INDICES, t0
162 	vluxei8.v	FEBA, (STATEP), INDICES
163 	vluxei8.v	HGDC, (STATEP_C), INDICES
166 	addi		NUM_BLOCKS, NUM_BLOCKS, -1
169 	vmv.v.v		PREV_FEBA, FEBA
170 	vmv.v.v		PREV_HGDC, HGDC
172 	// Load the next 512-bit message block and endian-swap each 32-bit word.
173 	vle32.v		W0, (DATA)
174 	vrev8.v		W0, W0
176 	vle32.v		W1, (DATA)
177 	vrev8.v		W1, W1
179 	vle32.v		W2, (DATA)
180 	vrev8.v		W2, W2
182 	vle32.v		W3, (DATA)
183 	vrev8.v		W3, W3
186 	// Do the 64 rounds of SHA-256.
200 	vsuxei8.v	FEBA, (STATEP), INDICES
201 	vsuxei8.v	HGDC, (STATEP_C), INDICES
225 .size K256, . - K256