Lines Matching +full:half +full:-

1 /* SPDX-License-Identifier: Apache-2.0 OR BSD-2-Clause */
3 // This file is dual-licensed, meaning that you can use it under your
39 // The generated code of this file depends on the following RISC-V extensions:
40 // - RV64I
41 // - RISC-V Vector ('V') with VLEN >= 128
42 // - RISC-V Vector Cryptography Bit-manipulation extension ('Zvkb')
87 	vror.vi		\d0, \d0, 32 - 16
88 	vror.vi		\d1, \d1, 32 - 16
89 	vror.vi		\d2, \d2, 32 - 16
90 	vror.vi		\d3, \d3, 32 - 16
101 	vror.vi		\b0, \b0, 32 - 12
102 	vror.vi		\b1, \b1, 32 - 12
103 	vror.vi		\b2, \b2, 32 - 12
104 	vror.vi		\b3, \b3, 32 - 12
115 	vror.vi		\d0, \d0, 32 - 8
116 	vror.vi		\d1, \d1, 32 - 8
117 	vror.vi		\d2, \d2, 32 - 8
118 	vror.vi		\d3, \d3, 32 - 8
129 	vror.vi		\b0, \b0, 32 - 7
130 	vror.vi		\b1, \b1, 32 - 7
131 	vror.vi		\b2, \b2, 32 - 7
132 	vror.vi		\b3, \b3, 32 - 7
139 // The counter is treated as 32-bit, following the RFC7539 convention.
143 	addi		sp, sp, -96
162 	li		CONSTS2, 0x79622d32	// "2-by" little endian
181 	// Set up the initial state matrix for the next VL blocks in v0-v15.
182 	// v{i} holds the i'th 32-bit word of the state matrix for all blocks.
202 	// Load the first half of the input data for each block into v16-v23.
203 	// v{16+i} holds the i'th 32-bit word for all blocks.
208 	addi		NROUNDS, NROUNDS, -2
217 	// Load the second half of the input data for each block into v24-v31.
218 	// v{24+i} holds the {8+i}'th 32-bit word for all blocks.
222 	// Finalize the first half of the keystream for each block.
232 	// Encrypt/decrypt the first half of the data for each block.
242 	// Store the first half of the output data for each block.
245 	// Finalize the second half of the keystream for each block.
257 	// Encrypt/decrypt the second half of the data for each block.
267 	// Store the second half of the output data for each block.