Lines Matching +full:12 +full:v
39 // The generated code of this file depends on the following RISC-V extensions:
41 // - RISC-V Vector ('V') with VLEN >= 128
42 // - RISC-V Vector Cryptography Bit-manipulation extension ('Zvkb')
92 // c += d; b ^= c; b = rol(b, 12);
101 vror.vi \b0, \b0, 32 - 12
102 vror.vi \b1, \b1, 32 - 12
103 vror.vi \b2, \b2, 32 - 12
104 vror.vi \b3, \b3, 32 - 12
167 lw KEY3, 12(KEYP)
175 lw NONCE2, 12(IVP)
182 // v{i} holds the i'th 32-bit word of the state matrix for all blocks.
183 // Note that only the counter word, at index 12, differs across blocks.
184 vmv.v.x v0, CONSTS0
185 vmv.v.x v1, CONSTS1
186 vmv.v.x v2, CONSTS2
187 vmv.v.x v3, CONSTS3
188 vmv.v.x v4, KEY0
189 vmv.v.x v5, KEY1
190 vmv.v.x v6, KEY2
191 vmv.v.x v7, KEY3
192 vmv.v.x v8, KEY4
193 vmv.v.x v9, KEY5
194 vmv.v.x v10, KEY6
195 vmv.v.x v11, KEY7
196 vid.v v12
198 vmv.v.x v13, NONCE0
199 vmv.v.x v14, NONCE1
200 vmv.v.x v15, NONCE2
203 // v{16+i} holds the i'th 32-bit word for all blocks.
204 vlsseg8e32.v v16, (INP), STRIDE
218 // v{24+i} holds the {8+i}'th 32-bit word for all blocks.
220 vlsseg8e32.v v24, (TMP), STRIDE
243 vssseg8e32.v v16, (OUTP), STRIDE
250 vid.v v0
269 vssseg8e32.v v24, (TMP), STRIDE