Lines Matching +full:dw +full:- +full:apb +full:- +full:ssi
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/clock/thead,th1520-clk-ap.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
18 timebase-frequency = <3000000>;
24 riscv,isa-base = "rv64i";
25 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
28 i-cache-block-size = <64>;
29 i-cache-size = <65536>;
30 i-cache-sets = <512>;
31 d-cache-block-size = <64>;
32 d-cache-size = <65536>;
33 d-cache-sets = <512>;
34 next-level-cache = <&l2_cache>;
35 mmu-type = "riscv,sv39";
37 cpu0_intc: interrupt-controller {
38 compatible = "riscv,cpu-intc";
39 interrupt-controller;
40 #interrupt-cells = <1>;
48 riscv,isa-base = "rv64i";
49 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
52 i-cache-block-size = <64>;
53 i-cache-size = <65536>;
54 i-cache-sets = <512>;
55 d-cache-block-size = <64>;
56 d-cache-size = <65536>;
57 d-cache-sets = <512>;
58 next-level-cache = <&l2_cache>;
59 mmu-type = "riscv,sv39";
61 cpu1_intc: interrupt-controller {
62 compatible = "riscv,cpu-intc";
63 interrupt-controller;
64 #interrupt-cells = <1>;
72 riscv,isa-base = "rv64i";
73 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
76 i-cache-block-size = <64>;
77 i-cache-size = <65536>;
78 i-cache-sets = <512>;
79 d-cache-block-size = <64>;
80 d-cache-size = <65536>;
81 d-cache-sets = <512>;
82 next-level-cache = <&l2_cache>;
83 mmu-type = "riscv,sv39";
85 cpu2_intc: interrupt-controller {
86 compatible = "riscv,cpu-intc";
87 interrupt-controller;
88 #interrupt-cells = <1>;
96 riscv,isa-base = "rv64i";
97 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
100 i-cache-block-size = <64>;
101 i-cache-size = <65536>;
102 i-cache-sets = <512>;
103 d-cache-block-size = <64>;
104 d-cache-size = <65536>;
105 d-cache-sets = <512>;
106 next-level-cache = <&l2_cache>;
107 mmu-type = "riscv,sv39";
109 cpu3_intc: interrupt-controller {
110 compatible = "riscv,cpu-intc";
111 interrupt-controller;
112 #interrupt-cells = <1>;
116 l2_cache: l2-cache {
118 cache-block-size = <64>;
119 cache-level = <2>;
120 cache-size = <1048576>;
121 cache-sets = <1024>;
122 cache-unified;
128 riscv,event-to-mhpmcounters =
145 riscv,event-to-mhpmevent =
162 riscv,raw-event-to-mhpmcounters =
208 compatible = "fixed-clock";
209 clock-output-names = "osc_24m";
210 #clock-cells = <0>;
213 osc_32k: 32k-oscillator {
214 compatible = "fixed-clock";
215 clock-output-names = "osc_32k";
216 #clock-cells = <0>;
220 compatible = "simple-bus";
221 interrupt-parent = <&plic>;
222 #address-cells = <2>;
223 #size-cells = <2>;
224 dma-noncoherent;
227 plic: interrupt-controller@ffd8000000 {
228 compatible = "thead,th1520-plic", "thead,c900-plic";
230 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
234 interrupt-controller;
235 #address-cells = <0>;
236 #interrupt-cells = <2>;
241 compatible = "thead,th1520-clint", "thead,c900-clint";
243 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
250 compatible = "thead,th1520-spi", "snps,dw-apb-ssi";
254 #address-cells = <1>;
255 #size-cells = <0>;
260 compatible = "snps,dw-apb-uart";
264 clock-names = "baudclk", "apb_pclk";
265 reg-shift = <2>;
266 reg-io-width = <4>;
271 compatible = "thead,th1520-dwcmshc";
275 clock-names = "core";
280 compatible = "thead,th1520-dwcmshc";
284 clock-names = "core";
289 compatible = "thead,th1520-dwcmshc";
293 clock-names = "core";
298 compatible = "snps,dw-apb-uart";
302 clock-names = "baudclk", "apb_pclk";
303 reg-shift = <2>;
304 reg-io-width = <4>;
309 compatible = "snps,dw-apb-uart";
313 clock-names = "baudclk", "apb_pclk";
314 reg-shift = <2>;
315 reg-io-width = <4>;
320 compatible = "snps,dw-apb-gpio";
322 #address-cells = <1>;
323 #size-cells = <0>;
326 portc: gpio-controller@0 {
327 compatible = "snps,dw-apb-gpio-port";
328 gpio-controller;
329 #gpio-cells = <2>;
332 interrupt-controller;
333 #interrupt-cells = <2>;
339 compatible = "snps,dw-apb-gpio";
341 #address-cells = <1>;
342 #size-cells = <0>;
345 portd: gpio-controller@0 {
346 compatible = "snps,dw-apb-gpio-port";
347 gpio-controller;
348 #gpio-cells = <2>;
351 interrupt-controller;
352 #interrupt-cells = <2>;
358 compatible = "snps,dw-apb-gpio";
360 #address-cells = <1>;
361 #size-cells = <0>;
364 porta: gpio-controller@0 {
365 compatible = "snps,dw-apb-gpio-port";
366 gpio-controller;
367 #gpio-cells = <2>;
370 interrupt-controller;
371 #interrupt-cells = <2>;
377 compatible = "snps,dw-apb-gpio";
379 #address-cells = <1>;
380 #size-cells = <0>;
383 portb: gpio-controller@0 {
384 compatible = "snps,dw-apb-gpio-port";
385 gpio-controller;
386 #gpio-cells = <2>;
389 interrupt-controller;
390 #interrupt-cells = <2>;
396 compatible = "snps,dw-apb-uart";
400 clock-names = "baudclk", "apb_pclk";
401 reg-shift = <2>;
402 reg-io-width = <4>;
406 clk: clock-controller@ffef010000 {
407 compatible = "thead,th1520-clk-ap";
410 #clock-cells = <1>;
413 dmac0: dma-controller@ffefc00000 {
414 compatible = "snps,axi-dma-1.01a";
418 clock-names = "core-clk", "cfgr-clk";
419 #dma-cells = <1>;
420 dma-channels = <4>;
421 snps,block-size = <65536 65536 65536 65536>;
423 snps,dma-masters = <1>;
424 snps,data-width = <4>;
425 snps,axi-max-burst-len = <16>;
430 compatible = "snps,dw-apb-timer";
433 clock-names = "timer";
439 compatible = "snps,dw-apb-timer";
442 clock-names = "timer";
448 compatible = "snps,dw-apb-timer";
451 clock-names = "timer";
457 compatible = "snps,dw-apb-timer";
460 clock-names = "timer";
466 compatible = "snps,dw-apb-uart";
470 clock-names = "baudclk", "apb_pclk";
471 reg-shift = <2>;
472 reg-io-width = <4>;
477 compatible = "snps,dw-apb-uart";
481 clock-names = "baudclk", "apb_pclk";
482 reg-shift = <2>;
483 reg-io-width = <4>;
488 compatible = "snps,dw-apb-timer";
491 clock-names = "timer";
497 compatible = "snps,dw-apb-timer";
500 clock-names = "timer";
506 compatible = "snps,dw-apb-timer";
509 clock-names = "timer";
515 compatible = "snps,dw-apb-timer";
518 clock-names = "timer";
524 compatible = "snps,dw-apb-gpio";
526 #address-cells = <1>;
527 #size-cells = <0>;
529 porte: gpio-controller@0 {
530 compatible = "snps,dw-apb-gpio-port";
531 gpio-controller;
532 #gpio-cells = <2>;
535 interrupt-controller;
536 #interrupt-cells = <2>;
542 compatible = "snps,dw-apb-gpio";
544 #address-cells = <1>;
545 #size-cells = <0>;
547 portf: gpio-controller@0 {
548 compatible = "snps,dw-apb-gpio-port";
549 gpio-controller;
550 #gpio-cells = <2>;
553 interrupt-controller;
554 #interrupt-cells = <2>;