Lines Matching +full:dw +full:- +full:apb +full:- +full:gpio
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/clock/thead,th1520-clk-ap.h>
9 #include <dt-bindings/power/thead,th1520-power.h>
10 #include <dt-bindings/reset/thead,th1520-reset.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
19 #size-cells = <0>;
20 timebase-frequency = <3000000>;
26 riscv,isa-base = "rv64i";
27 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
30 i-cache-block-size = <64>;
31 i-cache-size = <65536>;
32 i-cache-sets = <512>;
33 d-cache-block-size = <64>;
34 d-cache-size = <65536>;
35 d-cache-sets = <512>;
36 next-level-cache = <&l2_cache>;
37 mmu-type = "riscv,sv39";
39 cpu0_intc: interrupt-controller {
40 compatible = "riscv,cpu-intc";
41 interrupt-controller;
42 #interrupt-cells = <1>;
50 riscv,isa-base = "rv64i";
51 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
54 i-cache-block-size = <64>;
55 i-cache-size = <65536>;
56 i-cache-sets = <512>;
57 d-cache-block-size = <64>;
58 d-cache-size = <65536>;
59 d-cache-sets = <512>;
60 next-level-cache = <&l2_cache>;
61 mmu-type = "riscv,sv39";
63 cpu1_intc: interrupt-controller {
64 compatible = "riscv,cpu-intc";
65 interrupt-controller;
66 #interrupt-cells = <1>;
74 riscv,isa-base = "rv64i";
75 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
78 i-cache-block-size = <64>;
79 i-cache-size = <65536>;
80 i-cache-sets = <512>;
81 d-cache-block-size = <64>;
82 d-cache-size = <65536>;
83 d-cache-sets = <512>;
84 next-level-cache = <&l2_cache>;
85 mmu-type = "riscv,sv39";
87 cpu2_intc: interrupt-controller {
88 compatible = "riscv,cpu-intc";
89 interrupt-controller;
90 #interrupt-cells = <1>;
98 riscv,isa-base = "rv64i";
99 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
102 i-cache-block-size = <64>;
103 i-cache-size = <65536>;
104 i-cache-sets = <512>;
105 d-cache-block-size = <64>;
106 d-cache-size = <65536>;
107 d-cache-sets = <512>;
108 next-level-cache = <&l2_cache>;
109 mmu-type = "riscv,sv39";
111 cpu3_intc: interrupt-controller {
112 compatible = "riscv,cpu-intc";
113 interrupt-controller;
114 #interrupt-cells = <1>;
118 l2_cache: l2-cache {
120 cache-block-size = <64>;
121 cache-level = <2>;
122 cache-size = <1048576>;
123 cache-sets = <1024>;
124 cache-unified;
130 riscv,event-to-mhpmcounters =
147 riscv,event-to-mhpmevent =
164 riscv,raw-event-to-mhpmcounters =
210 compatible = "fixed-clock";
211 clock-output-names = "osc_24m";
212 #clock-cells = <0>;
215 osc_32k: 32k-oscillator {
216 compatible = "fixed-clock";
217 clock-output-names = "osc_32k";
218 #clock-cells = <0>;
221 aonsys_clk: clock-73728000 {
222 compatible = "fixed-clock";
223 clock-frequency = <73728000>;
224 clock-output-names = "aonsys_clk";
225 #clock-cells = <0>;
228 stmmac_axi_config: stmmac-axi-config {
235 compatible = "thead,th1520-aon";
237 mbox-names = "aon";
239 reset-names = "gpu-clkgen";
240 #power-domain-cells = <1>;
244 compatible = "simple-bus";
245 interrupt-parent = <&plic>;
246 #address-cells = <2>;
247 #size-cells = <2>;
248 dma-noncoherent;
251 plic: interrupt-controller@ffd8000000 {
252 compatible = "thead,th1520-plic", "thead,c900-plic";
254 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
258 interrupt-controller;
259 #address-cells = <0>;
260 #interrupt-cells = <2>;
265 compatible = "thead,th1520-clint", "thead,c900-clint";
267 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
274 compatible = "thead,th1520-spi", "snps,dw-apb-ssi";
278 #address-cells = <1>;
279 #size-cells = <0>;
284 compatible = "snps,dw-apb-uart";
288 clock-names = "baudclk", "apb_pclk";
289 reg-shift = <2>;
290 reg-io-width = <4>;
295 compatible = "thead,th1520-gmac", "snps,dwmac-3.70a";
297 reg-names = "dwmac", "apb";
299 interrupt-names = "macirq";
301 clock-names = "stmmaceth", "pclk";
303 snps,fixed-burst;
304 snps,multicast-filter-bins = <64>;
305 snps,perfect-filter-entries = <32>;
306 snps,axi-config = <&stmmac_axi_config>;
310 compatible = "snps,dwmac-mdio";
311 #address-cells = <1>;
312 #size-cells = <0>;
317 compatible = "thead,th1520-gmac", "snps,dwmac-3.70a";
319 reg-names = "dwmac", "apb";
321 interrupt-names = "macirq";
323 clock-names = "stmmaceth", "pclk";
325 snps,fixed-burst;
326 snps,multicast-filter-bins = <64>;
327 snps,perfect-filter-entries = <32>;
328 snps,axi-config = <&stmmac_axi_config>;
332 compatible = "snps,dwmac-mdio";
333 #address-cells = <1>;
334 #size-cells = <0>;
339 compatible = "thead,th1520-dwcmshc";
343 clock-names = "core";
348 compatible = "thead,th1520-dwcmshc";
352 clock-names = "core";
357 compatible = "thead,th1520-dwcmshc";
361 clock-names = "core";
366 compatible = "snps,dw-apb-uart";
370 clock-names = "baudclk", "apb_pclk";
371 reg-shift = <2>;
372 reg-io-width = <4>;
377 compatible = "snps,dw-apb-uart";
381 clock-names = "baudclk", "apb_pclk";
382 reg-shift = <2>;
383 reg-io-width = <4>;
387 gpio@ffe7f34000 {
388 compatible = "snps,dw-apb-gpio";
390 #address-cells = <1>;
391 #size-cells = <0>;
393 clock-names = "bus";
395 gpio2: gpio-controller@0 {
396 compatible = "snps,dw-apb-gpio-port";
397 gpio-controller;
398 #gpio-cells = <2>;
400 gpio-ranges = <&padctrl0_apsys 0 0 32>;
402 interrupt-controller;
403 #interrupt-cells = <2>;
408 gpio@ffe7f38000 {
409 compatible = "snps,dw-apb-gpio";
411 #address-cells = <1>;
412 #size-cells = <0>;
414 clock-names = "bus";
416 gpio3: gpio-controller@0 {
417 compatible = "snps,dw-apb-gpio-port";
418 gpio-controller;
419 #gpio-cells = <2>;
421 gpio-ranges = <&padctrl0_apsys 0 32 23>;
423 interrupt-controller;
424 #interrupt-cells = <2>;
430 compatible = "thead,th1520-pinctrl";
433 thead,pad-group = <2>;
436 gpio@ffec005000 {
437 compatible = "snps,dw-apb-gpio";
439 #address-cells = <1>;
440 #size-cells = <0>;
442 clock-names = "bus";
444 gpio0: gpio-controller@0 {
445 compatible = "snps,dw-apb-gpio-port";
446 gpio-controller;
447 #gpio-cells = <2>;
449 gpio-ranges = <&padctrl1_apsys 0 0 32>;
451 interrupt-controller;
452 #interrupt-cells = <2>;
457 gpio@ffec006000 {
458 compatible = "snps,dw-apb-gpio";
460 #address-cells = <1>;
461 #size-cells = <0>;
463 clock-names = "bus";
465 gpio1: gpio-controller@0 {
466 compatible = "snps,dw-apb-gpio-port";
467 gpio-controller;
468 #gpio-cells = <2>;
470 gpio-ranges = <&padctrl1_apsys 0 32 31>;
472 interrupt-controller;
473 #interrupt-cells = <2>;
479 compatible = "thead,th1520-pinctrl";
482 thead,pad-group = <3>;
486 compatible = "snps,dw-apb-uart";
490 clock-names = "baudclk", "apb_pclk";
491 reg-shift = <2>;
492 reg-io-width = <4>;
496 clk: clock-controller@ffef010000 {
497 compatible = "thead,th1520-clk-ap";
500 #clock-cells = <1>;
503 rst: reset-controller@ffef528000 {
504 compatible = "thead,th1520-reset";
506 #reset-cells = <1>;
509 clk_vo: clock-controller@ffef528050 {
510 compatible = "thead,th1520-clk-vo";
513 #clock-cells = <1>;
516 dmac0: dma-controller@ffefc00000 {
517 compatible = "snps,axi-dma-1.01a";
521 clock-names = "core-clk", "cfgr-clk";
522 #dma-cells = <1>;
523 dma-channels = <4>;
524 snps,block-size = <65536 65536 65536 65536>;
526 snps,dma-masters = <1>;
527 snps,data-width = <4>;
528 snps,axi-max-burst-len = <16>;
533 compatible = "snps,dw-apb-timer";
536 clock-names = "timer";
542 compatible = "snps,dw-apb-timer";
545 clock-names = "timer";
551 compatible = "snps,dw-apb-timer";
554 clock-names = "timer";
560 compatible = "snps,dw-apb-timer";
563 clock-names = "timer";
569 compatible = "snps,dw-apb-uart";
573 clock-names = "baudclk", "apb_pclk";
574 reg-shift = <2>;
575 reg-io-width = <4>;
580 compatible = "snps,dw-apb-uart";
584 clock-names = "baudclk", "apb_pclk";
585 reg-shift = <2>;
586 reg-io-width = <4>;
591 compatible = "snps,dw-apb-timer";
594 clock-names = "timer";
600 compatible = "snps,dw-apb-timer";
603 clock-names = "timer";
609 compatible = "snps,dw-apb-timer";
612 clock-names = "timer";
618 compatible = "snps,dw-apb-timer";
621 clock-names = "timer";
627 compatible = "thead,th1520-mbox";
632 reg-names = "local", "remote-icu0", "remote-icu1", "remote-icu2";
635 clock-names = "clk-local", "clk-remote-icu0", "clk-remote-icu1",
636 "clk-remote-icu2";
637 interrupt-parent = <&plic>;
639 #mbox-cells = <1>;
642 gpio@fffff41000 {
643 compatible = "snps,dw-apb-gpio";
645 #address-cells = <1>;
646 #size-cells = <0>;
648 aogpio: gpio-controller@0 {
649 compatible = "snps,dw-apb-gpio-port";
650 gpio-controller;
651 #gpio-cells = <2>;
653 gpio-ranges = <&padctrl_aosys 0 9 16>;
655 interrupt-controller;
656 #interrupt-cells = <2>;
662 compatible = "thead,th1520-pinctrl";
665 thead,pad-group = <1>;
674 reg-names = "common", "ts", "pd", "vm";
676 #thermal-sensor-cells = <1>;
679 gpio@fffff52000 {
680 compatible = "snps,dw-apb-gpio";
682 #address-cells = <1>;
683 #size-cells = <0>;
685 gpio4: gpio-controller@0 {
686 compatible = "snps,dw-apb-gpio-port";
687 gpio-controller;
688 #gpio-cells = <2>;
690 gpio-ranges = <&padctrl_aosys 0 25 22>, <&padctrl_aosys 22 7 1>;
692 interrupt-controller;
693 #interrupt-cells = <2>;