Lines Matching +full:k1 +full:- +full:syscon +full:- +full:mpmu
1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 #include <dt-bindings/clock/spacemit,k1-syscon.h>
8 /dts-v1/;
10 #address-cells = <2>;
11 #size-cells = <2>;
12 model = "SpacemiT K1";
13 compatible = "spacemit,k1";
16 #address-cells = <1>;
17 #size-cells = <0>;
18 timebase-frequency = <24000000>;
20 cpu-map {
57 riscv,isa-base = "rv64i";
58 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
63 riscv,cbom-block-size = <64>;
64 riscv,cbop-block-size = <64>;
65 riscv,cboz-block-size = <64>;
66 i-cache-block-size = <64>;
67 i-cache-size = <32768>;
68 i-cache-sets = <128>;
69 d-cache-block-size = <64>;
70 d-cache-size = <32768>;
71 d-cache-sets = <128>;
72 next-level-cache = <&cluster0_l2_cache>;
73 mmu-type = "riscv,sv39";
75 cpu0_intc: interrupt-controller {
76 compatible = "riscv,cpu-intc";
77 interrupt-controller;
78 #interrupt-cells = <1>;
87 riscv,isa-base = "rv64i";
88 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
93 riscv,cbom-block-size = <64>;
94 riscv,cbop-block-size = <64>;
95 riscv,cboz-block-size = <64>;
96 i-cache-block-size = <64>;
97 i-cache-size = <32768>;
98 i-cache-sets = <128>;
99 d-cache-block-size = <64>;
100 d-cache-size = <32768>;
101 d-cache-sets = <128>;
102 next-level-cache = <&cluster0_l2_cache>;
103 mmu-type = "riscv,sv39";
105 cpu1_intc: interrupt-controller {
106 compatible = "riscv,cpu-intc";
107 interrupt-controller;
108 #interrupt-cells = <1>;
117 riscv,isa-base = "rv64i";
118 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
123 riscv,cbom-block-size = <64>;
124 riscv,cbop-block-size = <64>;
125 riscv,cboz-block-size = <64>;
126 i-cache-block-size = <64>;
127 i-cache-size = <32768>;
128 i-cache-sets = <128>;
129 d-cache-block-size = <64>;
130 d-cache-size = <32768>;
131 d-cache-sets = <128>;
132 next-level-cache = <&cluster0_l2_cache>;
133 mmu-type = "riscv,sv39";
135 cpu2_intc: interrupt-controller {
136 compatible = "riscv,cpu-intc";
137 interrupt-controller;
138 #interrupt-cells = <1>;
147 riscv,isa-base = "rv64i";
148 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
153 riscv,cbom-block-size = <64>;
154 riscv,cbop-block-size = <64>;
155 riscv,cboz-block-size = <64>;
156 i-cache-block-size = <64>;
157 i-cache-size = <32768>;
158 i-cache-sets = <128>;
159 d-cache-block-size = <64>;
160 d-cache-size = <32768>;
161 d-cache-sets = <128>;
162 next-level-cache = <&cluster0_l2_cache>;
163 mmu-type = "riscv,sv39";
165 cpu3_intc: interrupt-controller {
166 compatible = "riscv,cpu-intc";
167 interrupt-controller;
168 #interrupt-cells = <1>;
177 riscv,isa-base = "rv64i";
178 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
183 riscv,cbom-block-size = <64>;
184 riscv,cbop-block-size = <64>;
185 riscv,cboz-block-size = <64>;
186 i-cache-block-size = <64>;
187 i-cache-size = <32768>;
188 i-cache-sets = <128>;
189 d-cache-block-size = <64>;
190 d-cache-size = <32768>;
191 d-cache-sets = <128>;
192 next-level-cache = <&cluster1_l2_cache>;
193 mmu-type = "riscv,sv39";
195 cpu4_intc: interrupt-controller {
196 compatible = "riscv,cpu-intc";
197 interrupt-controller;
198 #interrupt-cells = <1>;
207 riscv,isa-base = "rv64i";
208 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
213 riscv,cbom-block-size = <64>;
214 riscv,cbop-block-size = <64>;
215 riscv,cboz-block-size = <64>;
216 i-cache-block-size = <64>;
217 i-cache-size = <32768>;
218 i-cache-sets = <128>;
219 d-cache-block-size = <64>;
220 d-cache-size = <32768>;
221 d-cache-sets = <128>;
222 next-level-cache = <&cluster1_l2_cache>;
223 mmu-type = "riscv,sv39";
225 cpu5_intc: interrupt-controller {
226 compatible = "riscv,cpu-intc";
227 interrupt-controller;
228 #interrupt-cells = <1>;
237 riscv,isa-base = "rv64i";
238 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
243 riscv,cbom-block-size = <64>;
244 riscv,cbop-block-size = <64>;
245 riscv,cboz-block-size = <64>;
246 i-cache-block-size = <64>;
247 i-cache-size = <32768>;
248 i-cache-sets = <128>;
249 d-cache-block-size = <64>;
250 d-cache-size = <32768>;
251 d-cache-sets = <128>;
252 next-level-cache = <&cluster1_l2_cache>;
253 mmu-type = "riscv,sv39";
255 cpu6_intc: interrupt-controller {
256 compatible = "riscv,cpu-intc";
257 interrupt-controller;
258 #interrupt-cells = <1>;
267 riscv,isa-base = "rv64i";
268 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
273 riscv,cbom-block-size = <64>;
274 riscv,cbop-block-size = <64>;
275 riscv,cboz-block-size = <64>;
276 i-cache-block-size = <64>;
277 i-cache-size = <32768>;
278 i-cache-sets = <128>;
279 d-cache-block-size = <64>;
280 d-cache-size = <32768>;
281 d-cache-sets = <128>;
282 next-level-cache = <&cluster1_l2_cache>;
283 mmu-type = "riscv,sv39";
285 cpu7_intc: interrupt-controller {
286 compatible = "riscv,cpu-intc";
287 interrupt-controller;
288 #interrupt-cells = <1>;
292 cluster0_l2_cache: l2-cache0 {
294 cache-block-size = <64>;
295 cache-level = <2>;
296 cache-size = <524288>;
297 cache-sets = <512>;
298 cache-unified;
301 cluster1_l2_cache: l2-cache1 {
303 cache-block-size = <64>;
304 cache-level = <2>;
305 cache-size = <524288>;
306 cache-sets = <512>;
307 cache-unified;
312 vctcxo_1m: clock-1m {
313 compatible = "fixed-clock";
314 clock-frequency = <1000000>;
315 clock-output-names = "vctcxo_1m";
316 #clock-cells = <0>;
319 vctcxo_24m: clock-24m {
320 compatible = "fixed-clock";
321 clock-frequency = <24000000>;
322 clock-output-names = "vctcxo_24m";
323 #clock-cells = <0>;
326 vctcxo_3m: clock-3m {
327 compatible = "fixed-clock";
328 clock-frequency = <3000000>;
329 clock-output-names = "vctcxo_3m";
330 #clock-cells = <0>;
333 osc_32k: clock-32k {
334 compatible = "fixed-clock";
335 clock-frequency = <32000>;
336 clock-output-names = "osc_32k";
337 #clock-cells = <0>;
342 compatible = "simple-bus";
343 interrupt-parent = <&plic>;
344 #address-cells = <2>;
345 #size-cells = <2>;
346 dma-noncoherent;
349 syscon_rcpu: system-controller@c0880000 {
350 compatible = "spacemit,k1-syscon-rcpu";
352 #reset-cells = <1>;
355 syscon_rcpu2: system-controller@c0888000 {
356 compatible = "spacemit,k1-syscon-rcpu2";
358 #reset-cells = <1>;
361 syscon_apbc: system-controller@d4015000 {
362 compatible = "spacemit,k1-syscon-apbc";
366 clock-names = "osc", "vctcxo_1m", "vctcxo_3m",
368 #clock-cells = <1>;
369 #reset-cells = <1>;
373 compatible = "spacemit,k1-gpio";
377 clock-names = "core", "bus";
378 gpio-controller;
379 #gpio-cells = <3>;
381 interrupt-parent = <&plic>;
382 interrupt-controller;
383 #interrupt-cells = <3>;
384 gpio-ranges = <&pinctrl 0 0 0 32>,
391 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
393 #pwm-cells = <3>;
400 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
402 #pwm-cells = <3>;
409 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
411 #pwm-cells = <3>;
418 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
420 #pwm-cells = <3>;
427 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
429 #pwm-cells = <3>;
436 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
438 #pwm-cells = <3>;
445 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
447 #pwm-cells = <3>;
454 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
456 #pwm-cells = <3>;
463 compatible = "spacemit,k1-pinctrl";
467 clock-names = "func", "bus";
471 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
473 #pwm-cells = <3>;
480 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
482 #pwm-cells = <3>;
489 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
491 #pwm-cells = <3>;
498 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
500 #pwm-cells = <3>;
507 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
509 #pwm-cells = <3>;
516 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
518 #pwm-cells = <3>;
525 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
527 #pwm-cells = <3>;
534 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
536 #pwm-cells = <3>;
543 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
545 #pwm-cells = <3>;
552 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
554 #pwm-cells = <3>;
561 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
563 #pwm-cells = <3>;
570 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
572 #pwm-cells = <3>;
578 syscon_mpmu: system-controller@d4050000 {
579 compatible = "spacemit,k1-syscon-mpmu";
583 clock-names = "osc", "vctcxo_1m", "vctcxo_3m",
585 #clock-cells = <1>;
586 #power-domain-cells = <1>;
587 #reset-cells = <1>;
590 pll: clock-controller@d4090000 {
591 compatible = "spacemit,k1-pll";
594 spacemit,mpmu = <&syscon_mpmu>;
595 #clock-cells = <1>;
598 syscon_apmu: system-controller@d4282800 {
599 compatible = "spacemit,k1-syscon-apmu";
603 clock-names = "osc", "vctcxo_1m", "vctcxo_3m",
605 #clock-cells = <1>;
606 #power-domain-cells = <1>;
607 #reset-cells = <1>;
610 plic: interrupt-controller@e0000000 {
611 compatible = "spacemit,k1-plic", "sifive,plic-1.0.0";
613 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
621 interrupt-controller;
622 #address-cells = <0>;
623 #interrupt-cells = <1>;
628 compatible = "spacemit,k1-clint", "sifive,clint0";
630 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
640 syscon_apbc2: system-controller@f0610000 {
641 compatible = "spacemit,k1-syscon-apbc2";
643 #reset-cells = <1>;
646 camera-bus {
647 compatible = "simple-bus";
649 #address-cells = <2>;
650 #size-cells = <2>;
651 dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,
655 dma-bus {
656 compatible = "simple-bus";
658 #address-cells = <2>;
659 #size-cells = <2>;
660 dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,
664 compatible = "spacemit,k1-uart",
665 "intel,xscale-uart";
669 clock-names = "core", "bus";
671 reg-shift = <2>;
672 reg-io-width = <4>;
677 compatible = "spacemit,k1-uart",
678 "intel,xscale-uart";
682 clock-names = "core", "bus";
684 reg-shift = <2>;
685 reg-io-width = <4>;
690 compatible = "spacemit,k1-uart",
691 "intel,xscale-uart";
695 clock-names = "core", "bus";
697 reg-shift = <2>;
698 reg-io-width = <4>;
703 compatible = "spacemit,k1-uart",
704 "intel,xscale-uart";
708 clock-names = "core", "bus";
710 reg-shift = <2>;
711 reg-io-width = <4>;
716 compatible = "spacemit,k1-uart",
717 "intel,xscale-uart";
721 clock-names = "core", "bus";
723 reg-shift = <2>;
724 reg-io-width = <4>;
729 compatible = "spacemit,k1-uart",
730 "intel,xscale-uart";
734 clock-names = "core", "bus";
736 reg-shift = <2>;
737 reg-io-width = <4>;
742 compatible = "spacemit,k1-uart",
743 "intel,xscale-uart";
747 clock-names = "core", "bus";
749 reg-shift = <2>;
750 reg-io-width = <4>;
755 compatible = "spacemit,k1-uart",
756 "intel,xscale-uart";
760 clock-names = "core", "bus";
762 reg-shift = <2>;
763 reg-io-width = <4>;
768 compatible = "spacemit,k1-uart",
769 "intel,xscale-uart";
773 clock-names = "core", "bus";
775 reg-shift = <2>;
776 reg-io-width = <4>;
781 compatible = "spacemit,k1-uart",
782 "intel,xscale-uart";
785 clock-frequency = <14857000>;
786 reg-shift = <2>;
787 reg-io-width = <4>;
792 multimedia-bus {
793 compatible = "simple-bus";
795 #address-cells = <2>;
796 #size-cells = <2>;
797 dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,
801 network-bus {
802 compatible = "simple-bus";
804 #address-cells = <2>;
805 #size-cells = <2>;
806 dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,
810 pcie-bus {
811 compatible = "simple-bus";
813 #address-cells = <2>;
814 #size-cells = <2>;
815 dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,
819 storage-bus {
820 compatible = "simple-bus";
822 #address-cells = <2>;
823 #size-cells = <2>;
824 dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>;
827 compatible = "spacemit,k1-sdhci";
831 clock-names = "core", "io";