Lines Matching +full:cache +full:- +full:block
1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 #include <dt-bindings/clock/spacemit,k1-syscon.h>
8 /dts-v1/;
10 #address-cells = <2>;
11 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
18 timebase-frequency = <24000000>;
20 cpu-map {
57 riscv,isa-base = "rv64i";
58 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
63 riscv,cbom-block-size = <64>;
64 riscv,cbop-block-size = <64>;
65 riscv,cboz-block-size = <64>;
66 i-cache-block-size = <64>;
67 i-cache-size = <32768>;
68 i-cache-sets = <128>;
69 d-cache-block-size = <64>;
70 d-cache-size = <32768>;
71 d-cache-sets = <128>;
72 next-level-cache = <&cluster0_l2_cache>;
73 mmu-type = "riscv,sv39";
75 cpu0_intc: interrupt-controller {
76 compatible = "riscv,cpu-intc";
77 interrupt-controller;
78 #interrupt-cells = <1>;
87 riscv,isa-base = "rv64i";
88 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
93 riscv,cbom-block-size = <64>;
94 riscv,cbop-block-size = <64>;
95 riscv,cboz-block-size = <64>;
96 i-cache-block-size = <64>;
97 i-cache-size = <32768>;
98 i-cache-sets = <128>;
99 d-cache-block-size = <64>;
100 d-cache-size = <32768>;
101 d-cache-sets = <128>;
102 next-level-cache = <&cluster0_l2_cache>;
103 mmu-type = "riscv,sv39";
105 cpu1_intc: interrupt-controller {
106 compatible = "riscv,cpu-intc";
107 interrupt-controller;
108 #interrupt-cells = <1>;
117 riscv,isa-base = "rv64i";
118 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
123 riscv,cbom-block-size = <64>;
124 riscv,cbop-block-size = <64>;
125 riscv,cboz-block-size = <64>;
126 i-cache-block-size = <64>;
127 i-cache-size = <32768>;
128 i-cache-sets = <128>;
129 d-cache-block-size = <64>;
130 d-cache-size = <32768>;
131 d-cache-sets = <128>;
132 next-level-cache = <&cluster0_l2_cache>;
133 mmu-type = "riscv,sv39";
135 cpu2_intc: interrupt-controller {
136 compatible = "riscv,cpu-intc";
137 interrupt-controller;
138 #interrupt-cells = <1>;
147 riscv,isa-base = "rv64i";
148 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
153 riscv,cbom-block-size = <64>;
154 riscv,cbop-block-size = <64>;
155 riscv,cboz-block-size = <64>;
156 i-cache-block-size = <64>;
157 i-cache-size = <32768>;
158 i-cache-sets = <128>;
159 d-cache-block-size = <64>;
160 d-cache-size = <32768>;
161 d-cache-sets = <128>;
162 next-level-cache = <&cluster0_l2_cache>;
163 mmu-type = "riscv,sv39";
165 cpu3_intc: interrupt-controller {
166 compatible = "riscv,cpu-intc";
167 interrupt-controller;
168 #interrupt-cells = <1>;
177 riscv,isa-base = "rv64i";
178 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
183 riscv,cbom-block-size = <64>;
184 riscv,cbop-block-size = <64>;
185 riscv,cboz-block-size = <64>;
186 i-cache-block-size = <64>;
187 i-cache-size = <32768>;
188 i-cache-sets = <128>;
189 d-cache-block-size = <64>;
190 d-cache-size = <32768>;
191 d-cache-sets = <128>;
192 next-level-cache = <&cluster1_l2_cache>;
193 mmu-type = "riscv,sv39";
195 cpu4_intc: interrupt-controller {
196 compatible = "riscv,cpu-intc";
197 interrupt-controller;
198 #interrupt-cells = <1>;
207 riscv,isa-base = "rv64i";
208 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
213 riscv,cbom-block-size = <64>;
214 riscv,cbop-block-size = <64>;
215 riscv,cboz-block-size = <64>;
216 i-cache-block-size = <64>;
217 i-cache-size = <32768>;
218 i-cache-sets = <128>;
219 d-cache-block-size = <64>;
220 d-cache-size = <32768>;
221 d-cache-sets = <128>;
222 next-level-cache = <&cluster1_l2_cache>;
223 mmu-type = "riscv,sv39";
225 cpu5_intc: interrupt-controller {
226 compatible = "riscv,cpu-intc";
227 interrupt-controller;
228 #interrupt-cells = <1>;
237 riscv,isa-base = "rv64i";
238 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
243 riscv,cbom-block-size = <64>;
244 riscv,cbop-block-size = <64>;
245 riscv,cboz-block-size = <64>;
246 i-cache-block-size = <64>;
247 i-cache-size = <32768>;
248 i-cache-sets = <128>;
249 d-cache-block-size = <64>;
250 d-cache-size = <32768>;
251 d-cache-sets = <128>;
252 next-level-cache = <&cluster1_l2_cache>;
253 mmu-type = "riscv,sv39";
255 cpu6_intc: interrupt-controller {
256 compatible = "riscv,cpu-intc";
257 interrupt-controller;
258 #interrupt-cells = <1>;
267 riscv,isa-base = "rv64i";
268 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
273 riscv,cbom-block-size = <64>;
274 riscv,cbop-block-size = <64>;
275 riscv,cboz-block-size = <64>;
276 i-cache-block-size = <64>;
277 i-cache-size = <32768>;
278 i-cache-sets = <128>;
279 d-cache-block-size = <64>;
280 d-cache-size = <32768>;
281 d-cache-sets = <128>;
282 next-level-cache = <&cluster1_l2_cache>;
283 mmu-type = "riscv,sv39";
285 cpu7_intc: interrupt-controller {
286 compatible = "riscv,cpu-intc";
287 interrupt-controller;
288 #interrupt-cells = <1>;
292 cluster0_l2_cache: l2-cache0 {
293 compatible = "cache";
294 cache-block-size = <64>;
295 cache-level = <2>;
296 cache-size = <524288>;
297 cache-sets = <512>;
298 cache-unified;
301 cluster1_l2_cache: l2-cache1 {
302 compatible = "cache";
303 cache-block-size = <64>;
304 cache-level = <2>;
305 cache-size = <524288>;
306 cache-sets = <512>;
307 cache-unified;
312 vctcxo_1m: clock-1m {
313 compatible = "fixed-clock";
314 clock-frequency = <1000000>;
315 clock-output-names = "vctcxo_1m";
316 #clock-cells = <0>;
319 vctcxo_24m: clock-24m {
320 compatible = "fixed-clock";
321 clock-frequency = <24000000>;
322 clock-output-names = "vctcxo_24m";
323 #clock-cells = <0>;
326 vctcxo_3m: clock-3m {
327 compatible = "fixed-clock";
328 clock-frequency = <3000000>;
329 clock-output-names = "vctcxo_3m";
330 #clock-cells = <0>;
333 osc_32k: clock-32k {
334 compatible = "fixed-clock";
335 clock-frequency = <32000>;
336 clock-output-names = "osc_32k";
337 #clock-cells = <0>;
342 compatible = "simple-bus";
343 interrupt-parent = <&plic>;
344 #address-cells = <2>;
345 #size-cells = <2>;
346 dma-noncoherent;
349 syscon_rcpu: system-controller@c0880000 {
350 compatible = "spacemit,k1-syscon-rcpu";
352 #reset-cells = <1>;
355 syscon_rcpu2: system-controller@c0888000 {
356 compatible = "spacemit,k1-syscon-rcpu2";
358 #reset-cells = <1>;
362 compatible = "spacemit,k1-i2c";
364 #address-cells = <1>;
365 #size-cells = <0>;
368 clock-names = "func", "bus";
369 clock-frequency = <400000>;
375 compatible = "spacemit,k1-i2c";
377 #address-cells = <1>;
378 #size-cells = <0>;
381 clock-names = "func", "bus";
382 clock-frequency = <400000>;
388 compatible = "spacemit,k1-i2c";
390 #address-cells = <1>;
391 #size-cells = <0>;
394 clock-names = "func", "bus";
395 clock-frequency = <400000>;
401 compatible = "spacemit,k1-i2c";
403 #address-cells = <1>;
404 #size-cells = <0>;
407 clock-names = "func", "bus";
408 clock-frequency = <400000>;
414 compatible = "spacemit,k1-i2c";
416 #address-cells = <1>;
417 #size-cells = <0>;
420 clock-names = "func", "bus";
421 clock-frequency = <400000>;
426 syscon_apbc: system-controller@d4015000 {
427 compatible = "spacemit,k1-syscon-apbc";
431 clock-names = "osc", "vctcxo_1m", "vctcxo_3m",
433 #clock-cells = <1>;
434 #reset-cells = <1>;
438 compatible = "spacemit,k1-i2c";
440 #address-cells = <1>;
441 #size-cells = <0>;
444 clock-names = "func", "bus";
445 clock-frequency = <400000>;
451 compatible = "spacemit,k1-gpio";
455 clock-names = "core", "bus";
456 gpio-controller;
457 #gpio-cells = <3>;
459 interrupt-parent = <&plic>;
460 interrupt-controller;
461 #interrupt-cells = <3>;
462 gpio-ranges = <&pinctrl 0 0 0 32>,
469 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
471 #pwm-cells = <3>;
478 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
480 #pwm-cells = <3>;
487 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
489 #pwm-cells = <3>;
496 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
498 #pwm-cells = <3>;
505 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
507 #pwm-cells = <3>;
514 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
516 #pwm-cells = <3>;
523 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
525 #pwm-cells = <3>;
532 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
534 #pwm-cells = <3>;
541 compatible = "spacemit,k1-i2c";
543 #address-cells = <1>;
544 #size-cells = <0>;
547 clock-names = "func", "bus";
548 clock-frequency = <400000>;
554 compatible = "spacemit,k1-i2c";
556 #address-cells = <1>;
557 #size-cells = <0>;
560 clock-names = "func", "bus";
561 clock-frequency = <400000>;
567 compatible = "spacemit,k1-pinctrl";
571 clock-names = "func", "bus";
575 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
577 #pwm-cells = <3>;
584 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
586 #pwm-cells = <3>;
593 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
595 #pwm-cells = <3>;
602 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
604 #pwm-cells = <3>;
611 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
613 #pwm-cells = <3>;
620 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
622 #pwm-cells = <3>;
629 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
631 #pwm-cells = <3>;
638 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
640 #pwm-cells = <3>;
647 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
649 #pwm-cells = <3>;
656 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
658 #pwm-cells = <3>;
665 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
667 #pwm-cells = <3>;
674 compatible = "spacemit,k1-pwm", "marvell,pxa910-pwm";
676 #pwm-cells = <3>;
682 syscon_mpmu: system-controller@d4050000 {
683 compatible = "spacemit,k1-syscon-mpmu";
687 clock-names = "osc", "vctcxo_1m", "vctcxo_3m",
689 #clock-cells = <1>;
690 #power-domain-cells = <1>;
691 #reset-cells = <1>;
694 pll: clock-controller@d4090000 {
695 compatible = "spacemit,k1-pll";
699 #clock-cells = <1>;
702 syscon_apmu: system-controller@d4282800 {
703 compatible = "spacemit,k1-syscon-apmu";
707 clock-names = "osc", "vctcxo_1m", "vctcxo_3m",
709 #clock-cells = <1>;
710 #power-domain-cells = <1>;
711 #reset-cells = <1>;
714 plic: interrupt-controller@e0000000 {
715 compatible = "spacemit,k1-plic", "sifive,plic-1.0.0";
717 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
725 interrupt-controller;
726 #address-cells = <0>;
727 #interrupt-cells = <1>;
732 compatible = "spacemit,k1-clint", "sifive,clint0";
734 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
744 syscon_apbc2: system-controller@f0610000 {
745 compatible = "spacemit,k1-syscon-apbc2";
747 #reset-cells = <1>;
752 camera-bus {
753 compatible = "simple-bus";
755 #address-cells = <2>;
756 #size-cells = <2>;
757 dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,
761 dma-bus {
762 compatible = "simple-bus";
764 #address-cells = <2>;
765 #size-cells = <2>;
766 dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,
769 pdma: dma-controller@d4000000 {
770 compatible = "spacemit,k1-pdma";
775 dma-channels = <16>;
776 #dma-cells= <1>;
781 compatible = "spacemit,k1-uart",
782 "intel,xscale-uart";
786 clock-names = "core", "bus";
789 reg-shift = <2>;
790 reg-io-width = <4>;
795 compatible = "spacemit,k1-uart",
796 "intel,xscale-uart";
800 clock-names = "core", "bus";
803 reg-shift = <2>;
804 reg-io-width = <4>;
809 compatible = "spacemit,k1-uart",
810 "intel,xscale-uart";
814 clock-names = "core", "bus";
817 reg-shift = <2>;
818 reg-io-width = <4>;
823 compatible = "spacemit,k1-uart",
824 "intel,xscale-uart";
828 clock-names = "core", "bus";
831 reg-shift = <2>;
832 reg-io-width = <4>;
837 compatible = "spacemit,k1-uart",
838 "intel,xscale-uart";
842 clock-names = "core", "bus";
845 reg-shift = <2>;
846 reg-io-width = <4>;
851 compatible = "spacemit,k1-uart",
852 "intel,xscale-uart";
856 clock-names = "core", "bus";
859 reg-shift = <2>;
860 reg-io-width = <4>;
865 compatible = "spacemit,k1-uart",
866 "intel,xscale-uart";
870 clock-names = "core", "bus";
873 reg-shift = <2>;
874 reg-io-width = <4>;
879 compatible = "spacemit,k1-uart",
880 "intel,xscale-uart";
884 clock-names = "core", "bus";
887 reg-shift = <2>;
888 reg-io-width = <4>;
893 compatible = "spacemit,k1-uart",
894 "intel,xscale-uart";
898 clock-names = "core", "bus";
901 reg-shift = <2>;
902 reg-io-width = <4>;
907 compatible = "spacemit,k1-qspi";
908 #address-cells = <1>;
909 #size-cells = <0>;
912 reg-names = "QuadSPI", "QuadSPI-memory";
915 clock-names = "qspi_en", "qspi";
925 multimedia-bus {
926 compatible = "simple-bus";
928 #address-cells = <2>;
929 #size-cells = <2>;
930 dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,
934 network-bus {
935 compatible = "simple-bus";
937 #address-cells = <2>;
938 #size-cells = <2>;
939 dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,
943 compatible = "spacemit,k1-emac";
947 mac-address = [ 00 00 00 00 00 00 ];
954 compatible = "spacemit,k1-emac";
958 mac-address = [ 00 00 00 00 00 00 ];
965 pcie-bus {
966 compatible = "simple-bus";
968 #address-cells = <2>;
969 #size-cells = <2>;
970 dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,
974 storage-bus {
975 compatible = "simple-bus";
977 #address-cells = <2>;
978 #size-cells = <2>;
979 dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>;
982 compatible = "spacemit,k1-sdhci";
986 clock-names = "core", "io";