Lines Matching +full:cache +full:- +full:controller +full:- +full:0
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #address-cells = <2>;
8 #size-cells = <2>;
11 #address-cells = <1>;
12 #size-cells = <0>;
13 timebase-frequency = <50000000>;
15 cpu0: cpu@0 {
17 reg = <0>;
18 i-cache-block-size = <64>;
19 i-cache-size = <65536>;
20 i-cache-sets = <512>;
21 d-cache-block-size = <64>;
22 d-cache-size = <65536>;
23 d-cache-sets = <512>;
25 mmu-type = "riscv,sv48";
26 next-level-cache = <&l2_cache0>;
28 riscv,isa-base = "rv64i";
29 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
40 riscv,cbom-block-size = <64>;
41 riscv,cbop-block-size = <64>;
42 riscv,cboz-block-size = <64>;
44 cpu0_intc: interrupt-controller {
45 compatible = "riscv,cpu-intc";
46 interrupt-controller;
47 #interrupt-cells = <1>;
54 i-cache-block-size = <64>;
55 i-cache-size = <65536>;
56 i-cache-sets = <512>;
57 d-cache-block-size = <64>;
58 d-cache-size = <65536>;
59 d-cache-sets = <512>;
61 mmu-type = "riscv,sv48";
62 next-level-cache = <&l2_cache0>;
64 riscv,isa-base = "rv64i";
65 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
76 riscv,cbom-block-size = <64>;
77 riscv,cbop-block-size = <64>;
78 riscv,cboz-block-size = <64>;
80 cpu1_intc: interrupt-controller {
81 compatible = "riscv,cpu-intc";
82 interrupt-controller;
83 #interrupt-cells = <1>;
90 i-cache-block-size = <64>;
91 i-cache-size = <65536>;
92 i-cache-sets = <512>;
93 d-cache-block-size = <64>;
94 d-cache-size = <65536>;
95 d-cache-sets = <512>;
97 mmu-type = "riscv,sv48";
98 next-level-cache = <&l2_cache0>;
100 riscv,isa-base = "rv64i";
101 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
112 riscv,cbom-block-size = <64>;
113 riscv,cbop-block-size = <64>;
114 riscv,cboz-block-size = <64>;
116 cpu2_intc: interrupt-controller {
117 compatible = "riscv,cpu-intc";
118 interrupt-controller;
119 #interrupt-cells = <1>;
126 i-cache-block-size = <64>;
127 i-cache-size = <65536>;
128 i-cache-sets = <512>;
129 d-cache-block-size = <64>;
130 d-cache-size = <65536>;
131 d-cache-sets = <512>;
133 mmu-type = "riscv,sv48";
134 next-level-cache = <&l2_cache0>;
136 riscv,isa-base = "rv64i";
137 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
148 riscv,cbom-block-size = <64>;
149 riscv,cbop-block-size = <64>;
150 riscv,cboz-block-size = <64>;
152 cpu3_intc: interrupt-controller {
153 compatible = "riscv,cpu-intc";
154 interrupt-controller;
155 #interrupt-cells = <1>;
162 i-cache-block-size = <64>;
163 i-cache-size = <65536>;
164 i-cache-sets = <512>;
165 d-cache-block-size = <64>;
166 d-cache-size = <65536>;
167 d-cache-sets = <512>;
169 mmu-type = "riscv,sv48";
170 next-level-cache = <&l2_cache1>;
172 riscv,isa-base = "rv64i";
173 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
184 riscv,cbom-block-size = <64>;
185 riscv,cbop-block-size = <64>;
186 riscv,cboz-block-size = <64>;
188 cpu4_intc: interrupt-controller {
189 compatible = "riscv,cpu-intc";
190 interrupt-controller;
191 #interrupt-cells = <1>;
198 i-cache-block-size = <64>;
199 i-cache-size = <65536>;
200 i-cache-sets = <512>;
201 d-cache-block-size = <64>;
202 d-cache-size = <65536>;
203 d-cache-sets = <512>;
205 mmu-type = "riscv,sv48";
206 next-level-cache = <&l2_cache1>;
208 riscv,isa-base = "rv64i";
209 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
220 riscv,cbom-block-size = <64>;
221 riscv,cbop-block-size = <64>;
222 riscv,cboz-block-size = <64>;
224 cpu5_intc: interrupt-controller {
225 compatible = "riscv,cpu-intc";
226 interrupt-controller;
227 #interrupt-cells = <1>;
234 i-cache-block-size = <64>;
235 i-cache-size = <65536>;
236 i-cache-sets = <512>;
237 d-cache-block-size = <64>;
238 d-cache-size = <65536>;
239 d-cache-sets = <512>;
241 mmu-type = "riscv,sv48";
242 next-level-cache = <&l2_cache1>;
244 riscv,isa-base = "rv64i";
245 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
256 riscv,cbom-block-size = <64>;
257 riscv,cbop-block-size = <64>;
258 riscv,cboz-block-size = <64>;
260 cpu6_intc: interrupt-controller {
261 compatible = "riscv,cpu-intc";
262 interrupt-controller;
263 #interrupt-cells = <1>;
270 i-cache-block-size = <64>;
271 i-cache-size = <65536>;
272 i-cache-sets = <512>;
273 d-cache-block-size = <64>;
274 d-cache-size = <65536>;
275 d-cache-sets = <512>;
277 mmu-type = "riscv,sv48";
278 next-level-cache = <&l2_cache1>;
280 riscv,isa-base = "rv64i";
281 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
292 riscv,cbom-block-size = <64>;
293 riscv,cbop-block-size = <64>;
294 riscv,cboz-block-size = <64>;
296 cpu7_intc: interrupt-controller {
297 compatible = "riscv,cpu-intc";
298 interrupt-controller;
299 #interrupt-cells = <1>;
306 i-cache-block-size = <64>;
307 i-cache-size = <65536>;
308 i-cache-sets = <512>;
309 d-cache-block-size = <64>;
310 d-cache-size = <65536>;
311 d-cache-sets = <512>;
313 mmu-type = "riscv,sv48";
314 next-level-cache = <&l2_cache2>;
316 riscv,isa-base = "rv64i";
317 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
328 riscv,cbom-block-size = <64>;
329 riscv,cbop-block-size = <64>;
330 riscv,cboz-block-size = <64>;
332 cpu8_intc: interrupt-controller {
333 compatible = "riscv,cpu-intc";
334 interrupt-controller;
335 #interrupt-cells = <1>;
342 i-cache-block-size = <64>;
343 i-cache-size = <65536>;
344 i-cache-sets = <512>;
345 d-cache-block-size = <64>;
346 d-cache-size = <65536>;
347 d-cache-sets = <512>;
349 mmu-type = "riscv,sv48";
350 next-level-cache = <&l2_cache2>;
352 riscv,isa-base = "rv64i";
353 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
364 riscv,cbom-block-size = <64>;
365 riscv,cbop-block-size = <64>;
366 riscv,cboz-block-size = <64>;
368 cpu9_intc: interrupt-controller {
369 compatible = "riscv,cpu-intc";
370 interrupt-controller;
371 #interrupt-cells = <1>;
378 i-cache-block-size = <64>;
379 i-cache-size = <65536>;
380 i-cache-sets = <512>;
381 d-cache-block-size = <64>;
382 d-cache-size = <65536>;
383 d-cache-sets = <512>;
385 mmu-type = "riscv,sv48";
386 next-level-cache = <&l2_cache2>;
388 riscv,isa-base = "rv64i";
389 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
400 riscv,cbom-block-size = <64>;
401 riscv,cbop-block-size = <64>;
402 riscv,cboz-block-size = <64>;
404 cpu10_intc: interrupt-controller {
405 compatible = "riscv,cpu-intc";
406 interrupt-controller;
407 #interrupt-cells = <1>;
414 i-cache-block-size = <64>;
415 i-cache-size = <65536>;
416 i-cache-sets = <512>;
417 d-cache-block-size = <64>;
418 d-cache-size = <65536>;
419 d-cache-sets = <512>;
421 mmu-type = "riscv,sv48";
422 next-level-cache = <&l2_cache2>;
424 riscv,isa-base = "rv64i";
425 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
436 riscv,cbom-block-size = <64>;
437 riscv,cbop-block-size = <64>;
438 riscv,cboz-block-size = <64>;
440 cpu11_intc: interrupt-controller {
441 compatible = "riscv,cpu-intc";
442 interrupt-controller;
443 #interrupt-cells = <1>;
450 i-cache-block-size = <64>;
451 i-cache-size = <65536>;
452 i-cache-sets = <512>;
453 d-cache-block-size = <64>;
454 d-cache-size = <65536>;
455 d-cache-sets = <512>;
457 mmu-type = "riscv,sv48";
458 next-level-cache = <&l2_cache3>;
460 riscv,isa-base = "rv64i";
461 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
472 riscv,cbom-block-size = <64>;
473 riscv,cbop-block-size = <64>;
474 riscv,cboz-block-size = <64>;
476 cpu12_intc: interrupt-controller {
477 compatible = "riscv,cpu-intc";
478 interrupt-controller;
479 #interrupt-cells = <1>;
486 i-cache-block-size = <64>;
487 i-cache-size = <65536>;
488 i-cache-sets = <512>;
489 d-cache-block-size = <64>;
490 d-cache-size = <65536>;
491 d-cache-sets = <512>;
493 mmu-type = "riscv,sv48";
494 next-level-cache = <&l2_cache3>;
496 riscv,isa-base = "rv64i";
497 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
508 riscv,cbom-block-size = <64>;
509 riscv,cbop-block-size = <64>;
510 riscv,cboz-block-size = <64>;
512 cpu13_intc: interrupt-controller {
513 compatible = "riscv,cpu-intc";
514 interrupt-controller;
515 #interrupt-cells = <1>;
522 i-cache-block-size = <64>;
523 i-cache-size = <65536>;
524 i-cache-sets = <512>;
525 d-cache-block-size = <64>;
526 d-cache-size = <65536>;
527 d-cache-sets = <512>;
529 mmu-type = "riscv,sv48";
530 next-level-cache = <&l2_cache3>;
532 riscv,isa-base = "rv64i";
533 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
544 riscv,cbom-block-size = <64>;
545 riscv,cbop-block-size = <64>;
546 riscv,cboz-block-size = <64>;
548 cpu14_intc: interrupt-controller {
549 compatible = "riscv,cpu-intc";
550 interrupt-controller;
551 #interrupt-cells = <1>;
558 i-cache-block-size = <64>;
559 i-cache-size = <65536>;
560 i-cache-sets = <512>;
561 d-cache-block-size = <64>;
562 d-cache-size = <65536>;
563 d-cache-sets = <512>;
565 mmu-type = "riscv,sv48";
566 next-level-cache = <&l2_cache3>;
568 riscv,isa-base = "rv64i";
569 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
580 riscv,cbom-block-size = <64>;
581 riscv,cbop-block-size = <64>;
582 riscv,cboz-block-size = <64>;
584 cpu15_intc: interrupt-controller {
585 compatible = "riscv,cpu-intc";
586 interrupt-controller;
587 #interrupt-cells = <1>;
594 i-cache-block-size = <64>;
595 i-cache-size = <65536>;
596 i-cache-sets = <512>;
597 d-cache-block-size = <64>;
598 d-cache-size = <65536>;
599 d-cache-sets = <512>;
601 mmu-type = "riscv,sv48";
602 next-level-cache = <&l2_cache4>;
604 riscv,isa-base = "rv64i";
605 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
616 riscv,cbom-block-size = <64>;
617 riscv,cbop-block-size = <64>;
618 riscv,cboz-block-size = <64>;
620 cpu16_intc: interrupt-controller {
621 compatible = "riscv,cpu-intc";
622 interrupt-controller;
623 #interrupt-cells = <1>;
630 i-cache-block-size = <64>;
631 i-cache-size = <65536>;
632 i-cache-sets = <512>;
633 d-cache-block-size = <64>;
634 d-cache-size = <65536>;
635 d-cache-sets = <512>;
637 mmu-type = "riscv,sv48";
638 next-level-cache = <&l2_cache4>;
640 riscv,isa-base = "rv64i";
641 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
652 riscv,cbom-block-size = <64>;
653 riscv,cbop-block-size = <64>;
654 riscv,cboz-block-size = <64>;
656 cpu17_intc: interrupt-controller {
657 compatible = "riscv,cpu-intc";
658 interrupt-controller;
659 #interrupt-cells = <1>;
666 i-cache-block-size = <64>;
667 i-cache-size = <65536>;
668 i-cache-sets = <512>;
669 d-cache-block-size = <64>;
670 d-cache-size = <65536>;
671 d-cache-sets = <512>;
673 mmu-type = "riscv,sv48";
674 next-level-cache = <&l2_cache4>;
676 riscv,isa-base = "rv64i";
677 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
688 riscv,cbom-block-size = <64>;
689 riscv,cbop-block-size = <64>;
690 riscv,cboz-block-size = <64>;
692 cpu18_intc: interrupt-controller {
693 compatible = "riscv,cpu-intc";
694 interrupt-controller;
695 #interrupt-cells = <1>;
702 i-cache-block-size = <64>;
703 i-cache-size = <65536>;
704 i-cache-sets = <512>;
705 d-cache-block-size = <64>;
706 d-cache-size = <65536>;
707 d-cache-sets = <512>;
709 mmu-type = "riscv,sv48";
710 next-level-cache = <&l2_cache4>;
712 riscv,isa-base = "rv64i";
713 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
724 riscv,cbom-block-size = <64>;
725 riscv,cbop-block-size = <64>;
726 riscv,cboz-block-size = <64>;
728 cpu19_intc: interrupt-controller {
729 compatible = "riscv,cpu-intc";
730 interrupt-controller;
731 #interrupt-cells = <1>;
738 i-cache-block-size = <64>;
739 i-cache-size = <65536>;
740 i-cache-sets = <512>;
741 d-cache-block-size = <64>;
742 d-cache-size = <65536>;
743 d-cache-sets = <512>;
745 mmu-type = "riscv,sv48";
746 next-level-cache = <&l2_cache5>;
748 riscv,isa-base = "rv64i";
749 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
760 riscv,cbom-block-size = <64>;
761 riscv,cbop-block-size = <64>;
762 riscv,cboz-block-size = <64>;
764 cpu20_intc: interrupt-controller {
765 compatible = "riscv,cpu-intc";
766 interrupt-controller;
767 #interrupt-cells = <1>;
774 i-cache-block-size = <64>;
775 i-cache-size = <65536>;
776 i-cache-sets = <512>;
777 d-cache-block-size = <64>;
778 d-cache-size = <65536>;
779 d-cache-sets = <512>;
781 mmu-type = "riscv,sv48";
782 next-level-cache = <&l2_cache5>;
784 riscv,isa-base = "rv64i";
785 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
796 riscv,cbom-block-size = <64>;
797 riscv,cbop-block-size = <64>;
798 riscv,cboz-block-size = <64>;
800 cpu21_intc: interrupt-controller {
801 compatible = "riscv,cpu-intc";
802 interrupt-controller;
803 #interrupt-cells = <1>;
810 i-cache-block-size = <64>;
811 i-cache-size = <65536>;
812 i-cache-sets = <512>;
813 d-cache-block-size = <64>;
814 d-cache-size = <65536>;
815 d-cache-sets = <512>;
817 mmu-type = "riscv,sv48";
818 next-level-cache = <&l2_cache5>;
820 riscv,isa-base = "rv64i";
821 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
832 riscv,cbom-block-size = <64>;
833 riscv,cbop-block-size = <64>;
834 riscv,cboz-block-size = <64>;
836 cpu22_intc: interrupt-controller {
837 compatible = "riscv,cpu-intc";
838 interrupt-controller;
839 #interrupt-cells = <1>;
846 i-cache-block-size = <64>;
847 i-cache-size = <65536>;
848 i-cache-sets = <512>;
849 d-cache-block-size = <64>;
850 d-cache-size = <65536>;
851 d-cache-sets = <512>;
853 mmu-type = "riscv,sv48";
854 next-level-cache = <&l2_cache5>;
856 riscv,isa-base = "rv64i";
857 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
868 riscv,cbom-block-size = <64>;
869 riscv,cbop-block-size = <64>;
870 riscv,cboz-block-size = <64>;
872 cpu23_intc: interrupt-controller {
873 compatible = "riscv,cpu-intc";
874 interrupt-controller;
875 #interrupt-cells = <1>;
882 i-cache-block-size = <64>;
883 i-cache-size = <65536>;
884 i-cache-sets = <512>;
885 d-cache-block-size = <64>;
886 d-cache-size = <65536>;
887 d-cache-sets = <512>;
889 mmu-type = "riscv,sv48";
890 next-level-cache = <&l2_cache6>;
892 riscv,isa-base = "rv64i";
893 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
904 riscv,cbom-block-size = <64>;
905 riscv,cbop-block-size = <64>;
906 riscv,cboz-block-size = <64>;
908 cpu24_intc: interrupt-controller {
909 compatible = "riscv,cpu-intc";
910 interrupt-controller;
911 #interrupt-cells = <1>;
918 i-cache-block-size = <64>;
919 i-cache-size = <65536>;
920 i-cache-sets = <512>;
921 d-cache-block-size = <64>;
922 d-cache-size = <65536>;
923 d-cache-sets = <512>;
925 mmu-type = "riscv,sv48";
926 next-level-cache = <&l2_cache6>;
928 riscv,isa-base = "rv64i";
929 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
940 riscv,cbom-block-size = <64>;
941 riscv,cbop-block-size = <64>;
942 riscv,cboz-block-size = <64>;
944 cpu25_intc: interrupt-controller {
945 compatible = "riscv,cpu-intc";
946 interrupt-controller;
947 #interrupt-cells = <1>;
954 i-cache-block-size = <64>;
955 i-cache-size = <65536>;
956 i-cache-sets = <512>;
957 d-cache-block-size = <64>;
958 d-cache-size = <65536>;
959 d-cache-sets = <512>;
961 mmu-type = "riscv,sv48";
962 next-level-cache = <&l2_cache6>;
964 riscv,isa-base = "rv64i";
965 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
976 riscv,cbom-block-size = <64>;
977 riscv,cbop-block-size = <64>;
978 riscv,cboz-block-size = <64>;
980 cpu26_intc: interrupt-controller {
981 compatible = "riscv,cpu-intc";
982 interrupt-controller;
983 #interrupt-cells = <1>;
990 i-cache-block-size = <64>;
991 i-cache-size = <65536>;
992 i-cache-sets = <512>;
993 d-cache-block-size = <64>;
994 d-cache-size = <65536>;
995 d-cache-sets = <512>;
997 mmu-type = "riscv,sv48";
998 next-level-cache = <&l2_cache6>;
1000 riscv,isa-base = "rv64i";
1001 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1012 riscv,cbom-block-size = <64>;
1013 riscv,cbop-block-size = <64>;
1014 riscv,cboz-block-size = <64>;
1016 cpu27_intc: interrupt-controller {
1017 compatible = "riscv,cpu-intc";
1018 interrupt-controller;
1019 #interrupt-cells = <1>;
1026 i-cache-block-size = <64>;
1027 i-cache-size = <65536>;
1028 i-cache-sets = <512>;
1029 d-cache-block-size = <64>;
1030 d-cache-size = <65536>;
1031 d-cache-sets = <512>;
1033 mmu-type = "riscv,sv48";
1034 next-level-cache = <&l2_cache7>;
1036 riscv,isa-base = "rv64i";
1037 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1048 riscv,cbom-block-size = <64>;
1049 riscv,cbop-block-size = <64>;
1050 riscv,cboz-block-size = <64>;
1052 cpu28_intc: interrupt-controller {
1053 compatible = "riscv,cpu-intc";
1054 interrupt-controller;
1055 #interrupt-cells = <1>;
1062 i-cache-block-size = <64>;
1063 i-cache-size = <65536>;
1064 i-cache-sets = <512>;
1065 d-cache-block-size = <64>;
1066 d-cache-size = <65536>;
1067 d-cache-sets = <512>;
1069 mmu-type = "riscv,sv48";
1070 next-level-cache = <&l2_cache7>;
1072 riscv,isa-base = "rv64i";
1073 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1084 riscv,cbom-block-size = <64>;
1085 riscv,cbop-block-size = <64>;
1086 riscv,cboz-block-size = <64>;
1088 cpu29_intc: interrupt-controller {
1089 compatible = "riscv,cpu-intc";
1090 interrupt-controller;
1091 #interrupt-cells = <1>;
1098 i-cache-block-size = <64>;
1099 i-cache-size = <65536>;
1100 i-cache-sets = <512>;
1101 d-cache-block-size = <64>;
1102 d-cache-size = <65536>;
1103 d-cache-sets = <512>;
1105 mmu-type = "riscv,sv48";
1106 next-level-cache = <&l2_cache7>;
1108 riscv,isa-base = "rv64i";
1109 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1120 riscv,cbom-block-size = <64>;
1121 riscv,cbop-block-size = <64>;
1122 riscv,cboz-block-size = <64>;
1124 cpu30_intc: interrupt-controller {
1125 compatible = "riscv,cpu-intc";
1126 interrupt-controller;
1127 #interrupt-cells = <1>;
1134 i-cache-block-size = <64>;
1135 i-cache-size = <65536>;
1136 i-cache-sets = <512>;
1137 d-cache-block-size = <64>;
1138 d-cache-size = <65536>;
1139 d-cache-sets = <512>;
1141 mmu-type = "riscv,sv48";
1142 next-level-cache = <&l2_cache7>;
1144 riscv,isa-base = "rv64i";
1145 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1156 riscv,cbom-block-size = <64>;
1157 riscv,cbop-block-size = <64>;
1158 riscv,cboz-block-size = <64>;
1160 cpu31_intc: interrupt-controller {
1161 compatible = "riscv,cpu-intc";
1162 interrupt-controller;
1163 #interrupt-cells = <1>;
1170 i-cache-block-size = <64>;
1171 i-cache-size = <65536>;
1172 i-cache-sets = <512>;
1173 d-cache-block-size = <64>;
1174 d-cache-size = <65536>;
1175 d-cache-sets = <512>;
1177 mmu-type = "riscv,sv48";
1178 next-level-cache = <&l2_cache8>;
1180 riscv,isa-base = "rv64i";
1181 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1192 riscv,cbom-block-size = <64>;
1193 riscv,cbop-block-size = <64>;
1194 riscv,cboz-block-size = <64>;
1196 cpu32_intc: interrupt-controller {
1197 compatible = "riscv,cpu-intc";
1198 interrupt-controller;
1199 #interrupt-cells = <1>;
1206 i-cache-block-size = <64>;
1207 i-cache-size = <65536>;
1208 i-cache-sets = <512>;
1209 d-cache-block-size = <64>;
1210 d-cache-size = <65536>;
1211 d-cache-sets = <512>;
1213 mmu-type = "riscv,sv48";
1214 next-level-cache = <&l2_cache8>;
1216 riscv,isa-base = "rv64i";
1217 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1228 riscv,cbom-block-size = <64>;
1229 riscv,cbop-block-size = <64>;
1230 riscv,cboz-block-size = <64>;
1232 cpu33_intc: interrupt-controller {
1233 compatible = "riscv,cpu-intc";
1234 interrupt-controller;
1235 #interrupt-cells = <1>;
1242 i-cache-block-size = <64>;
1243 i-cache-size = <65536>;
1244 i-cache-sets = <512>;
1245 d-cache-block-size = <64>;
1246 d-cache-size = <65536>;
1247 d-cache-sets = <512>;
1249 mmu-type = "riscv,sv48";
1250 next-level-cache = <&l2_cache8>;
1252 riscv,isa-base = "rv64i";
1253 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1264 riscv,cbom-block-size = <64>;
1265 riscv,cbop-block-size = <64>;
1266 riscv,cboz-block-size = <64>;
1268 cpu34_intc: interrupt-controller {
1269 compatible = "riscv,cpu-intc";
1270 interrupt-controller;
1271 #interrupt-cells = <1>;
1278 i-cache-block-size = <64>;
1279 i-cache-size = <65536>;
1280 i-cache-sets = <512>;
1281 d-cache-block-size = <64>;
1282 d-cache-size = <65536>;
1283 d-cache-sets = <512>;
1285 mmu-type = "riscv,sv48";
1286 next-level-cache = <&l2_cache8>;
1288 riscv,isa-base = "rv64i";
1289 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1300 riscv,cbom-block-size = <64>;
1301 riscv,cbop-block-size = <64>;
1302 riscv,cboz-block-size = <64>;
1304 cpu35_intc: interrupt-controller {
1305 compatible = "riscv,cpu-intc";
1306 interrupt-controller;
1307 #interrupt-cells = <1>;
1314 i-cache-block-size = <64>;
1315 i-cache-size = <65536>;
1316 i-cache-sets = <512>;
1317 d-cache-block-size = <64>;
1318 d-cache-size = <65536>;
1319 d-cache-sets = <512>;
1321 mmu-type = "riscv,sv48";
1322 next-level-cache = <&l2_cache9>;
1324 riscv,isa-base = "rv64i";
1325 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1336 riscv,cbom-block-size = <64>;
1337 riscv,cbop-block-size = <64>;
1338 riscv,cboz-block-size = <64>;
1340 cpu36_intc: interrupt-controller {
1341 compatible = "riscv,cpu-intc";
1342 interrupt-controller;
1343 #interrupt-cells = <1>;
1350 i-cache-block-size = <64>;
1351 i-cache-size = <65536>;
1352 i-cache-sets = <512>;
1353 d-cache-block-size = <64>;
1354 d-cache-size = <65536>;
1355 d-cache-sets = <512>;
1357 mmu-type = "riscv,sv48";
1358 next-level-cache = <&l2_cache9>;
1360 riscv,isa-base = "rv64i";
1361 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1372 riscv,cbom-block-size = <64>;
1373 riscv,cbop-block-size = <64>;
1374 riscv,cboz-block-size = <64>;
1376 cpu37_intc: interrupt-controller {
1377 compatible = "riscv,cpu-intc";
1378 interrupt-controller;
1379 #interrupt-cells = <1>;
1386 i-cache-block-size = <64>;
1387 i-cache-size = <65536>;
1388 i-cache-sets = <512>;
1389 d-cache-block-size = <64>;
1390 d-cache-size = <65536>;
1391 d-cache-sets = <512>;
1393 mmu-type = "riscv,sv48";
1394 next-level-cache = <&l2_cache9>;
1396 riscv,isa-base = "rv64i";
1397 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1408 riscv,cbom-block-size = <64>;
1409 riscv,cbop-block-size = <64>;
1410 riscv,cboz-block-size = <64>;
1412 cpu38_intc: interrupt-controller {
1413 compatible = "riscv,cpu-intc";
1414 interrupt-controller;
1415 #interrupt-cells = <1>;
1422 i-cache-block-size = <64>;
1423 i-cache-size = <65536>;
1424 i-cache-sets = <512>;
1425 d-cache-block-size = <64>;
1426 d-cache-size = <65536>;
1427 d-cache-sets = <512>;
1429 mmu-type = "riscv,sv48";
1430 next-level-cache = <&l2_cache9>;
1432 riscv,isa-base = "rv64i";
1433 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1444 riscv,cbom-block-size = <64>;
1445 riscv,cbop-block-size = <64>;
1446 riscv,cboz-block-size = <64>;
1448 cpu39_intc: interrupt-controller {
1449 compatible = "riscv,cpu-intc";
1450 interrupt-controller;
1451 #interrupt-cells = <1>;
1458 i-cache-block-size = <64>;
1459 i-cache-size = <65536>;
1460 i-cache-sets = <512>;
1461 d-cache-block-size = <64>;
1462 d-cache-size = <65536>;
1463 d-cache-sets = <512>;
1465 mmu-type = "riscv,sv48";
1466 next-level-cache = <&l2_cache10>;
1468 riscv,isa-base = "rv64i";
1469 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1480 riscv,cbom-block-size = <64>;
1481 riscv,cbop-block-size = <64>;
1482 riscv,cboz-block-size = <64>;
1484 cpu40_intc: interrupt-controller {
1485 compatible = "riscv,cpu-intc";
1486 interrupt-controller;
1487 #interrupt-cells = <1>;
1494 i-cache-block-size = <64>;
1495 i-cache-size = <65536>;
1496 i-cache-sets = <512>;
1497 d-cache-block-size = <64>;
1498 d-cache-size = <65536>;
1499 d-cache-sets = <512>;
1501 mmu-type = "riscv,sv48";
1502 next-level-cache = <&l2_cache10>;
1504 riscv,isa-base = "rv64i";
1505 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1516 riscv,cbom-block-size = <64>;
1517 riscv,cbop-block-size = <64>;
1518 riscv,cboz-block-size = <64>;
1520 cpu41_intc: interrupt-controller {
1521 compatible = "riscv,cpu-intc";
1522 interrupt-controller;
1523 #interrupt-cells = <1>;
1530 i-cache-block-size = <64>;
1531 i-cache-size = <65536>;
1532 i-cache-sets = <512>;
1533 d-cache-block-size = <64>;
1534 d-cache-size = <65536>;
1535 d-cache-sets = <512>;
1537 mmu-type = "riscv,sv48";
1538 next-level-cache = <&l2_cache10>;
1540 riscv,isa-base = "rv64i";
1541 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1552 riscv,cbom-block-size = <64>;
1553 riscv,cbop-block-size = <64>;
1554 riscv,cboz-block-size = <64>;
1556 cpu42_intc: interrupt-controller {
1557 compatible = "riscv,cpu-intc";
1558 interrupt-controller;
1559 #interrupt-cells = <1>;
1566 i-cache-block-size = <64>;
1567 i-cache-size = <65536>;
1568 i-cache-sets = <512>;
1569 d-cache-block-size = <64>;
1570 d-cache-size = <65536>;
1571 d-cache-sets = <512>;
1573 mmu-type = "riscv,sv48";
1574 next-level-cache = <&l2_cache10>;
1576 riscv,isa-base = "rv64i";
1577 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1588 riscv,cbom-block-size = <64>;
1589 riscv,cbop-block-size = <64>;
1590 riscv,cboz-block-size = <64>;
1592 cpu43_intc: interrupt-controller {
1593 compatible = "riscv,cpu-intc";
1594 interrupt-controller;
1595 #interrupt-cells = <1>;
1602 i-cache-block-size = <64>;
1603 i-cache-size = <65536>;
1604 i-cache-sets = <512>;
1605 d-cache-block-size = <64>;
1606 d-cache-size = <65536>;
1607 d-cache-sets = <512>;
1609 mmu-type = "riscv,sv48";
1610 next-level-cache = <&l2_cache11>;
1612 riscv,isa-base = "rv64i";
1613 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1624 riscv,cbom-block-size = <64>;
1625 riscv,cbop-block-size = <64>;
1626 riscv,cboz-block-size = <64>;
1628 cpu44_intc: interrupt-controller {
1629 compatible = "riscv,cpu-intc";
1630 interrupt-controller;
1631 #interrupt-cells = <1>;
1638 i-cache-block-size = <64>;
1639 i-cache-size = <65536>;
1640 i-cache-sets = <512>;
1641 d-cache-block-size = <64>;
1642 d-cache-size = <65536>;
1643 d-cache-sets = <512>;
1645 mmu-type = "riscv,sv48";
1646 next-level-cache = <&l2_cache11>;
1648 riscv,isa-base = "rv64i";
1649 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1660 riscv,cbom-block-size = <64>;
1661 riscv,cbop-block-size = <64>;
1662 riscv,cboz-block-size = <64>;
1664 cpu45_intc: interrupt-controller {
1665 compatible = "riscv,cpu-intc";
1666 interrupt-controller;
1667 #interrupt-cells = <1>;
1674 i-cache-block-size = <64>;
1675 i-cache-size = <65536>;
1676 i-cache-sets = <512>;
1677 d-cache-block-size = <64>;
1678 d-cache-size = <65536>;
1679 d-cache-sets = <512>;
1681 mmu-type = "riscv,sv48";
1682 next-level-cache = <&l2_cache11>;
1684 riscv,isa-base = "rv64i";
1685 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1696 riscv,cbom-block-size = <64>;
1697 riscv,cbop-block-size = <64>;
1698 riscv,cboz-block-size = <64>;
1700 cpu46_intc: interrupt-controller {
1701 compatible = "riscv,cpu-intc";
1702 interrupt-controller;
1703 #interrupt-cells = <1>;
1710 i-cache-block-size = <64>;
1711 i-cache-size = <65536>;
1712 i-cache-sets = <512>;
1713 d-cache-block-size = <64>;
1714 d-cache-size = <65536>;
1715 d-cache-sets = <512>;
1717 mmu-type = "riscv,sv48";
1718 next-level-cache = <&l2_cache11>;
1720 riscv,isa-base = "rv64i";
1721 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1732 riscv,cbom-block-size = <64>;
1733 riscv,cbop-block-size = <64>;
1734 riscv,cboz-block-size = <64>;
1736 cpu47_intc: interrupt-controller {
1737 compatible = "riscv,cpu-intc";
1738 interrupt-controller;
1739 #interrupt-cells = <1>;
1746 i-cache-block-size = <64>;
1747 i-cache-size = <65536>;
1748 i-cache-sets = <512>;
1749 d-cache-block-size = <64>;
1750 d-cache-size = <65536>;
1751 d-cache-sets = <512>;
1753 mmu-type = "riscv,sv48";
1754 next-level-cache = <&l2_cache12>;
1756 riscv,isa-base = "rv64i";
1757 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1768 riscv,cbom-block-size = <64>;
1769 riscv,cbop-block-size = <64>;
1770 riscv,cboz-block-size = <64>;
1772 cpu48_intc: interrupt-controller {
1773 compatible = "riscv,cpu-intc";
1774 interrupt-controller;
1775 #interrupt-cells = <1>;
1782 i-cache-block-size = <64>;
1783 i-cache-size = <65536>;
1784 i-cache-sets = <512>;
1785 d-cache-block-size = <64>;
1786 d-cache-size = <65536>;
1787 d-cache-sets = <512>;
1789 mmu-type = "riscv,sv48";
1790 next-level-cache = <&l2_cache12>;
1792 riscv,isa-base = "rv64i";
1793 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1804 riscv,cbom-block-size = <64>;
1805 riscv,cbop-block-size = <64>;
1806 riscv,cboz-block-size = <64>;
1808 cpu49_intc: interrupt-controller {
1809 compatible = "riscv,cpu-intc";
1810 interrupt-controller;
1811 #interrupt-cells = <1>;
1818 i-cache-block-size = <64>;
1819 i-cache-size = <65536>;
1820 i-cache-sets = <512>;
1821 d-cache-block-size = <64>;
1822 d-cache-size = <65536>;
1823 d-cache-sets = <512>;
1825 mmu-type = "riscv,sv48";
1826 next-level-cache = <&l2_cache12>;
1828 riscv,isa-base = "rv64i";
1829 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1840 riscv,cbom-block-size = <64>;
1841 riscv,cbop-block-size = <64>;
1842 riscv,cboz-block-size = <64>;
1844 cpu50_intc: interrupt-controller {
1845 compatible = "riscv,cpu-intc";
1846 interrupt-controller;
1847 #interrupt-cells = <1>;
1854 i-cache-block-size = <64>;
1855 i-cache-size = <65536>;
1856 i-cache-sets = <512>;
1857 d-cache-block-size = <64>;
1858 d-cache-size = <65536>;
1859 d-cache-sets = <512>;
1861 mmu-type = "riscv,sv48";
1862 next-level-cache = <&l2_cache12>;
1864 riscv,isa-base = "rv64i";
1865 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1876 riscv,cbom-block-size = <64>;
1877 riscv,cbop-block-size = <64>;
1878 riscv,cboz-block-size = <64>;
1880 cpu51_intc: interrupt-controller {
1881 compatible = "riscv,cpu-intc";
1882 interrupt-controller;
1883 #interrupt-cells = <1>;
1890 i-cache-block-size = <64>;
1891 i-cache-size = <65536>;
1892 i-cache-sets = <512>;
1893 d-cache-block-size = <64>;
1894 d-cache-size = <65536>;
1895 d-cache-sets = <512>;
1897 mmu-type = "riscv,sv48";
1898 next-level-cache = <&l2_cache13>;
1900 riscv,isa-base = "rv64i";
1901 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1912 riscv,cbom-block-size = <64>;
1913 riscv,cbop-block-size = <64>;
1914 riscv,cboz-block-size = <64>;
1916 cpu52_intc: interrupt-controller {
1917 compatible = "riscv,cpu-intc";
1918 interrupt-controller;
1919 #interrupt-cells = <1>;
1926 i-cache-block-size = <64>;
1927 i-cache-size = <65536>;
1928 i-cache-sets = <512>;
1929 d-cache-block-size = <64>;
1930 d-cache-size = <65536>;
1931 d-cache-sets = <512>;
1933 mmu-type = "riscv,sv48";
1934 next-level-cache = <&l2_cache13>;
1936 riscv,isa-base = "rv64i";
1937 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1948 riscv,cbom-block-size = <64>;
1949 riscv,cbop-block-size = <64>;
1950 riscv,cboz-block-size = <64>;
1952 cpu53_intc: interrupt-controller {
1953 compatible = "riscv,cpu-intc";
1954 interrupt-controller;
1955 #interrupt-cells = <1>;
1962 i-cache-block-size = <64>;
1963 i-cache-size = <65536>;
1964 i-cache-sets = <512>;
1965 d-cache-block-size = <64>;
1966 d-cache-size = <65536>;
1967 d-cache-sets = <512>;
1969 mmu-type = "riscv,sv48";
1970 next-level-cache = <&l2_cache13>;
1972 riscv,isa-base = "rv64i";
1973 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1984 riscv,cbom-block-size = <64>;
1985 riscv,cbop-block-size = <64>;
1986 riscv,cboz-block-size = <64>;
1988 cpu54_intc: interrupt-controller {
1989 compatible = "riscv,cpu-intc";
1990 interrupt-controller;
1991 #interrupt-cells = <1>;
1998 i-cache-block-size = <64>;
1999 i-cache-size = <65536>;
2000 i-cache-sets = <512>;
2001 d-cache-block-size = <64>;
2002 d-cache-size = <65536>;
2003 d-cache-sets = <512>;
2005 mmu-type = "riscv,sv48";
2006 next-level-cache = <&l2_cache13>;
2008 riscv,isa-base = "rv64i";
2009 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
2020 riscv,cbom-block-size = <64>;
2021 riscv,cbop-block-size = <64>;
2022 riscv,cboz-block-size = <64>;
2024 cpu55_intc: interrupt-controller {
2025 compatible = "riscv,cpu-intc";
2026 interrupt-controller;
2027 #interrupt-cells = <1>;
2034 i-cache-block-size = <64>;
2035 i-cache-size = <65536>;
2036 i-cache-sets = <512>;
2037 d-cache-block-size = <64>;
2038 d-cache-size = <65536>;
2039 d-cache-sets = <512>;
2041 mmu-type = "riscv,sv48";
2042 next-level-cache = <&l2_cache14>;
2044 riscv,isa-base = "rv64i";
2045 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
2056 riscv,cbom-block-size = <64>;
2057 riscv,cbop-block-size = <64>;
2058 riscv,cboz-block-size = <64>;
2060 cpu56_intc: interrupt-controller {
2061 compatible = "riscv,cpu-intc";
2062 interrupt-controller;
2063 #interrupt-cells = <1>;
2070 i-cache-block-size = <64>;
2071 i-cache-size = <65536>;
2072 i-cache-sets = <512>;
2073 d-cache-block-size = <64>;
2074 d-cache-size = <65536>;
2075 d-cache-sets = <512>;
2077 mmu-type = "riscv,sv48";
2078 next-level-cache = <&l2_cache14>;
2080 riscv,isa-base = "rv64i";
2081 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
2092 riscv,cbom-block-size = <64>;
2093 riscv,cbop-block-size = <64>;
2094 riscv,cboz-block-size = <64>;
2096 cpu57_intc: interrupt-controller {
2097 compatible = "riscv,cpu-intc";
2098 interrupt-controller;
2099 #interrupt-cells = <1>;
2106 i-cache-block-size = <64>;
2107 i-cache-size = <65536>;
2108 i-cache-sets = <512>;
2109 d-cache-block-size = <64>;
2110 d-cache-size = <65536>;
2111 d-cache-sets = <512>;
2113 mmu-type = "riscv,sv48";
2114 next-level-cache = <&l2_cache14>;
2116 riscv,isa-base = "rv64i";
2117 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
2128 riscv,cbom-block-size = <64>;
2129 riscv,cbop-block-size = <64>;
2130 riscv,cboz-block-size = <64>;
2132 cpu58_intc: interrupt-controller {
2133 compatible = "riscv,cpu-intc";
2134 interrupt-controller;
2135 #interrupt-cells = <1>;
2142 i-cache-block-size = <64>;
2143 i-cache-size = <65536>;
2144 i-cache-sets = <512>;
2145 d-cache-block-size = <64>;
2146 d-cache-size = <65536>;
2147 d-cache-sets = <512>;
2149 mmu-type = "riscv,sv48";
2150 next-level-cache = <&l2_cache14>;
2152 riscv,isa-base = "rv64i";
2153 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
2164 riscv,cbom-block-size = <64>;
2165 riscv,cbop-block-size = <64>;
2166 riscv,cboz-block-size = <64>;
2168 cpu59_intc: interrupt-controller {
2169 compatible = "riscv,cpu-intc";
2170 interrupt-controller;
2171 #interrupt-cells = <1>;
2178 i-cache-block-size = <64>;
2179 i-cache-size = <65536>;
2180 i-cache-sets = <512>;
2181 d-cache-block-size = <64>;
2182 d-cache-size = <65536>;
2183 d-cache-sets = <512>;
2185 mmu-type = "riscv,sv48";
2186 next-level-cache = <&l2_cache15>;
2188 riscv,isa-base = "rv64i";
2189 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
2200 riscv,cbom-block-size = <64>;
2201 riscv,cbop-block-size = <64>;
2202 riscv,cboz-block-size = <64>;
2204 cpu60_intc: interrupt-controller {
2205 compatible = "riscv,cpu-intc";
2206 interrupt-controller;
2207 #interrupt-cells = <1>;
2214 i-cache-block-size = <64>;
2215 i-cache-size = <65536>;
2216 i-cache-sets = <512>;
2217 d-cache-block-size = <64>;
2218 d-cache-size = <65536>;
2219 d-cache-sets = <512>;
2221 mmu-type = "riscv,sv48";
2222 next-level-cache = <&l2_cache15>;
2224 riscv,isa-base = "rv64i";
2225 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
2236 riscv,cbom-block-size = <64>;
2237 riscv,cbop-block-size = <64>;
2238 riscv,cboz-block-size = <64>;
2240 cpu61_intc: interrupt-controller {
2241 compatible = "riscv,cpu-intc";
2242 interrupt-controller;
2243 #interrupt-cells = <1>;
2250 i-cache-block-size = <64>;
2251 i-cache-size = <65536>;
2252 i-cache-sets = <512>;
2253 d-cache-block-size = <64>;
2254 d-cache-size = <65536>;
2255 d-cache-sets = <512>;
2257 mmu-type = "riscv,sv48";
2258 next-level-cache = <&l2_cache15>;
2260 riscv,isa-base = "rv64i";
2261 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
2272 riscv,cbom-block-size = <64>;
2273 riscv,cbop-block-size = <64>;
2274 riscv,cboz-block-size = <64>;
2276 cpu62_intc: interrupt-controller {
2277 compatible = "riscv,cpu-intc";
2278 interrupt-controller;
2279 #interrupt-cells = <1>;
2286 i-cache-block-size = <64>;
2287 i-cache-size = <65536>;
2288 i-cache-sets = <512>;
2289 d-cache-block-size = <64>;
2290 d-cache-size = <65536>;
2291 d-cache-sets = <512>;
2293 mmu-type = "riscv,sv48";
2294 next-level-cache = <&l2_cache15>;
2296 riscv,isa-base = "rv64i";
2297 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
2308 riscv,cbom-block-size = <64>;
2309 riscv,cbop-block-size = <64>;
2310 riscv,cboz-block-size = <64>;
2312 cpu63_intc: interrupt-controller {
2313 compatible = "riscv,cpu-intc";
2314 interrupt-controller;
2315 #interrupt-cells = <1>;
2319 cpu-map {
2611 l2_cache0: cache-controller-0 {
2612 compatible = "cache";
2613 cache-block-size = <64>;
2614 cache-level = <2>;
2615 cache-size = <2097152>;
2616 cache-sets = <2048>;
2617 cache-unified;
2618 next-level-cache = <&l3_cache>;
2621 l2_cache1: cache-controller-1 {
2622 compatible = "cache";
2623 cache-block-size = <64>;
2624 cache-level = <2>;
2625 cache-size = <2097152>;
2626 cache-sets = <2048>;
2627 cache-unified;
2628 next-level-cache = <&l3_cache>;
2631 l2_cache2: cache-controller-2 {
2632 compatible = "cache";
2633 cache-block-size = <64>;
2634 cache-level = <2>;
2635 cache-size = <2097152>;
2636 cache-sets = <2048>;
2637 cache-unified;
2638 next-level-cache = <&l3_cache>;
2641 l2_cache3: cache-controller-3 {
2642 compatible = "cache";
2643 cache-block-size = <64>;
2644 cache-level = <2>;
2645 cache-size = <2097152>;
2646 cache-sets = <2048>;
2647 cache-unified;
2648 next-level-cache = <&l3_cache>;
2651 l2_cache4: cache-controller-4 {
2652 compatible = "cache";
2653 cache-block-size = <64>;
2654 cache-level = <2>;
2655 cache-size = <2097152>;
2656 cache-sets = <2048>;
2657 cache-unified;
2658 next-level-cache = <&l3_cache>;
2661 l2_cache5: cache-controller-5 {
2662 compatible = "cache";
2663 cache-block-size = <64>;
2664 cache-level = <2>;
2665 cache-size = <2097152>;
2666 cache-sets = <2048>;
2667 cache-unified;
2668 next-level-cache = <&l3_cache>;
2671 l2_cache6: cache-controller-6 {
2672 compatible = "cache";
2673 cache-block-size = <64>;
2674 cache-level = <2>;
2675 cache-size = <2097152>;
2676 cache-sets = <2048>;
2677 cache-unified;
2678 next-level-cache = <&l3_cache>;
2681 l2_cache7: cache-controller-7 {
2682 compatible = "cache";
2683 cache-block-size = <64>;
2684 cache-level = <2>;
2685 cache-size = <2097152>;
2686 cache-sets = <2048>;
2687 cache-unified;
2688 next-level-cache = <&l3_cache>;
2691 l2_cache8: cache-controller-8 {
2692 compatible = "cache";
2693 cache-block-size = <64>;
2694 cache-level = <2>;
2695 cache-size = <2097152>;
2696 cache-sets = <2048>;
2697 cache-unified;
2698 next-level-cache = <&l3_cache>;
2701 l2_cache9: cache-controller-9 {
2702 compatible = "cache";
2703 cache-block-size = <64>;
2704 cache-level = <2>;
2705 cache-size = <2097152>;
2706 cache-sets = <2048>;
2707 cache-unified;
2708 next-level-cache = <&l3_cache>;
2711 l2_cache10: cache-controller-10 {
2712 compatible = "cache";
2713 cache-block-size = <64>;
2714 cache-level = <2>;
2715 cache-size = <2097152>;
2716 cache-sets = <2048>;
2717 cache-unified;
2718 next-level-cache = <&l3_cache>;
2721 l2_cache11: cache-controller-11 {
2722 compatible = "cache";
2723 cache-block-size = <64>;
2724 cache-level = <2>;
2725 cache-size = <2097152>;
2726 cache-sets = <2048>;
2727 cache-unified;
2728 next-level-cache = <&l3_cache>;
2731 l2_cache12: cache-controller-12 {
2732 compatible = "cache";
2733 cache-block-size = <64>;
2734 cache-level = <2>;
2735 cache-size = <2097152>;
2736 cache-sets = <2048>;
2737 cache-unified;
2738 next-level-cache = <&l3_cache>;
2741 l2_cache13: cache-controller-13 {
2742 compatible = "cache";
2743 cache-block-size = <64>;
2744 cache-level = <2>;
2745 cache-size = <2097152>;
2746 cache-sets = <2048>;
2747 cache-unified;
2748 next-level-cache = <&l3_cache>;
2751 l2_cache14: cache-controller-14 {
2752 compatible = "cache";
2753 cache-block-size = <64>;
2754 cache-level = <2>;
2755 cache-size = <2097152>;
2756 cache-sets = <2048>;
2757 cache-unified;
2758 next-level-cache = <&l3_cache>;
2761 l2_cache15: cache-controller-15 {
2762 compatible = "cache";
2763 cache-block-size = <64>;
2764 cache-level = <2>;
2765 cache-size = <2097152>;
2766 cache-sets = <2048>;
2767 cache-unified;
2768 next-level-cache = <&l3_cache>;
2771 l3_cache: cache-controller-16 {
2772 compatible = "cache";
2773 cache-block-size = <64>;
2774 cache-level = <3>;
2775 cache-size = <67108864>;
2776 cache-sets = <4096>;
2777 cache-unified;
2783 riscv,event-to-mhpmevent =
2784 <0x00003 0x00000000 0x00000010>,
2785 <0x00004 0x00000000 0x00000011>,
2786 <0x00005 0x00000000 0x00000007>,
2787 <0x00006 0x00000000 0x00000006>,
2788 <0x00008 0x00000000 0x00000027>,
2789 <0x00009 0x00000000 0x00000028>,
2790 <0x10000 0x00000000 0x0000000c>,
2791 <0x10001 0x00000000 0x0000000d>,
2792 <0x10002 0x00000000 0x0000000e>,
2793 <0x10003 0x00000000 0x0000000f>,
2794 <0x10008 0x00000000 0x00000001>,
2795 <0x10009 0x00000000 0x00000002>,
2796 <0x10010 0x00000000 0x00000010>,
2797 <0x10011 0x00000000 0x00000011>,
2798 <0x10012 0x00000000 0x00000012>,
2799 <0x10013 0x00000000 0x00000013>,
2800 <0x10019 0x00000000 0x00000004>,
2801 <0x10021 0x00000000 0x00000003>,
2802 <0x10030 0x00000000 0x0000001c>,
2803 <0x10031 0x00000000 0x0000001b>;
2804 riscv,event-to-mhpmcounters =
2805 <0x00003 0x00003 0xfffffff8>,
2806 <0x00004 0x00004 0xfffffff8>,
2807 <0x00005 0x00005 0xfffffff8>,
2808 <0x00006 0x00006 0xfffffff8>,
2809 <0x00007 0x00007 0xfffffff8>,
2810 <0x00008 0x00008 0xfffffff8>,
2811 <0x00009 0x00009 0xfffffff8>,
2812 <0x0000a 0x0000a 0xfffffff8>,
2813 <0x10000 0x10000 0xfffffff8>,
2814 <0x10001 0x10001 0xfffffff8>,
2815 <0x10002 0x10002 0xfffffff8>,
2816 <0x10003 0x10003 0xfffffff8>,
2817 <0x10008 0x10008 0xfffffff8>,
2818 <0x10009 0x10009 0xfffffff8>,
2819 <0x10010 0x10010 0xfffffff8>,
2820 <0x10011 0x10011 0xfffffff8>,
2821 <0x10012 0x10012 0xfffffff8>,
2822 <0x10013 0x10013 0xfffffff8>,
2823 <0x10019 0x10019 0xfffffff8>,
2824 <0x10021 0x10021 0xfffffff8>,
2825 <0x10030 0x10030 0xfffffff8>,
2826 <0x10031 0x10031 0xfffffff8>;
2827 riscv,raw-event-to-mhpmcounters =
2828 <0x00000000 0x00000001 0xffffffff 0xffffffff 0xfffffff8>,
2829 <0x00000000 0x00000002 0xffffffff 0xffffffff 0xfffffff8>,
2830 <0x00000000 0x00000003 0xffffffff 0xffffffff 0xfffffff8>,
2831 <0x00000000 0x00000004 0xffffffff 0xffffffff 0xfffffff8>,
2832 <0x00000000 0x00000005 0xffffffff 0xffffffff 0xfffffff8>,
2833 <0x00000000 0x00000006 0xffffffff 0xffffffff 0xfffffff8>,
2834 <0x00000000 0x00000007 0xffffffff 0xffffffff 0xfffffff8>,
2835 <0x00000000 0x00000008 0xffffffff 0xffffffff 0xfffffff8>,
2836 <0x00000000 0x00000009 0xffffffff 0xffffffff 0xfffffff8>,
2837 <0x00000000 0x0000000a 0xffffffff 0xffffffff 0xfffffff8>,
2838 <0x00000000 0x0000000b 0xffffffff 0xffffffff 0xfffffff8>,
2839 <0x00000000 0x0000000c 0xffffffff 0xffffffff 0xfffffff8>,
2840 <0x00000000 0x0000000d 0xffffffff 0xffffffff 0xfffffff8>,
2841 <0x00000000 0x0000000e 0xffffffff 0xffffffff 0xfffffff8>,
2842 <0x00000000 0x0000000f 0xffffffff 0xffffffff 0xfffffff8>,
2843 <0x00000000 0x00000010 0xffffffff 0xffffffff 0xfffffff8>,
2844 <0x00000000 0x00000011 0xffffffff 0xffffffff 0xfffffff8>,
2845 <0x00000000 0x00000012 0xffffffff 0xffffffff 0xfffffff8>,
2846 <0x00000000 0x00000013 0xffffffff 0xffffffff 0xfffffff8>,
2847 <0x00000000 0x00000014 0xffffffff 0xffffffff 0xfffffff8>,
2848 <0x00000000 0x00000015 0xffffffff 0xffffffff 0xfffffff8>,
2849 <0x00000000 0x00000016 0xffffffff 0xffffffff 0xfffffff8>,
2850 <0x00000000 0x00000017 0xffffffff 0xffffffff 0xfffffff8>,
2851 <0x00000000 0x00000018 0xffffffff 0xffffffff 0xfffffff8>,
2852 <0x00000000 0x00000019 0xffffffff 0xffffffff 0xfffffff8>,
2853 <0x00000000 0x0000001a 0xffffffff 0xffffffff 0xfffffff8>,
2854 <0x00000000 0x0000001b 0xffffffff 0xffffffff 0xfffffff8>,
2855 <0x00000000 0x0000001c 0xffffffff 0xffffffff 0xfffffff8>,
2856 <0x00000000 0x0000001d 0xffffffff 0xffffffff 0xfffffff8>,
2857 <0x00000000 0x0000001e 0xffffffff 0xffffffff 0xfffffff8>,
2858 <0x00000000 0x0000001f 0xffffffff 0xffffffff 0xfffffff8>,
2859 <0x00000000 0x00000020 0xffffffff 0xffffffff 0xfffffff8>,
2860 <0x00000000 0x00000021 0xffffffff 0xffffffff 0xfffffff8>,
2861 <0x00000000 0x00000022 0xffffffff 0xffffffff 0xfffffff8>,
2862 <0x00000000 0x00000023 0xffffffff 0xffffffff 0xfffffff8>,
2863 <0x00000000 0x00000024 0xffffffff 0xffffffff 0xfffffff8>,
2864 <0x00000000 0x00000025 0xffffffff 0xffffffff 0xfffffff8>,
2865 <0x00000000 0x00000026 0xffffffff 0xffffffff 0xfffffff8>,
2866 <0x00000000 0x00000027 0xffffffff 0xffffffff 0xfffffff8>,
2867 <0x00000000 0x00000028 0xffffffff 0xffffffff 0xfffffff8>,
2868 <0x00000000 0x00000029 0xffffffff 0xffffffff 0xfffffff8>,
2869 <0x00000000 0x0000002a 0xffffffff 0xffffffff 0xfffffff8>;
2873 intc: interrupt-controller@6d40000000 {
2874 compatible = "sophgo,sg2044-plic", "thead,c900-plic";
2875 #address-cells = <0>;
2876 #interrupt-cells = <2>;
2877 reg = <0x6d 0x40000000 0x0 0x4000000>;
2878 interrupt-controller;
2879 interrupts-extended =
2947 aclint_mswi: interrupt-controller@6d44000000 {
2948 compatible = "sophgo,sg2044-aclint-mswi", "thead,c900-aclint-mswi";
2949 reg = <0x6d 0x44000000 0x0 0x4000>;
2950 interrupts-extended = <&cpu0_intc 3>,
3017 compatible = "sophgo,sg2044-aclint-mtimer", "thead,c900-aclint-mtimer";
3018 reg = <0x6d 0x44004000 0x0 0x8000>;
3019 reg-names = "mtimecmp";
3020 interrupts-extended = <&cpu0_intc 7>,
3086 aclint_sswi: interrupt-controller@6d4400c000 {
3087 compatible = "sophgo,sg2044-aclint-sswi", "thead,c900-aclint-sswi";
3088 reg = <0x6d 0x4400c000 0x0 0x1000>;
3089 #interrupt-cells = <0>;
3090 interrupt-controller;
3091 interrupts-extended = <&cpu0_intc 1>,