Lines Matching +full:designware +full:- +full:i2c
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/clock/sophgo,sg2042-clkgen.h>
8 #include <dt-bindings/clock/sophgo,sg2042-pll.h>
9 #include <dt-bindings/clock/sophgo,sg2042-rpgate.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/pinctrl/pinctrl-sg2042.h>
12 #include <dt-bindings/reset/sophgo,sg2042-reset.h>
14 #include "sg2042-cpus.dtsi"
18 #address-cells = <2>;
19 #size-cells = <2>;
20 dma-noncoherent;
27 compatible = "fixed-clock";
28 clock-output-names = "cgi_main";
29 #clock-cells = <0>;
33 compatible = "fixed-clock";
34 clock-output-names = "cgi_dpll0";
35 #clock-cells = <0>;
39 compatible = "fixed-clock";
40 clock-output-names = "cgi_dpll1";
41 #clock-cells = <0>;
45 compatible = "simple-bus";
46 #address-cells = <2>;
47 #size-cells = <2>;
48 interrupt-parent = <&intc>;
51 i2c0: i2c@7030005000 {
52 compatible = "snps,designware-i2c";
54 #address-cells = <1>;
55 #size-cells = <0>;
57 clock-names = "ref";
58 clock-frequency = <100000>;
64 i2c1: i2c@7030006000 {
65 compatible = "snps,designware-i2c";
67 #address-cells = <1>;
68 #size-cells = <0>;
70 clock-names = "ref";
71 clock-frequency = <100000>;
77 i2c2: i2c@7030007000 {
78 compatible = "snps,designware-i2c";
80 #address-cells = <1>;
81 #size-cells = <0>;
83 clock-names = "ref";
84 clock-frequency = <100000>;
90 i2c3: i2c@7030008000 {
91 compatible = "snps,designware-i2c";
93 #address-cells = <1>;
94 #size-cells = <0>;
96 clock-names = "ref";
97 clock-frequency = <100000>;
104 compatible = "snps,dw-apb-gpio";
106 #address-cells = <1>;
107 #size-cells = <0>;
110 clock-names = "bus", "db";
112 port0a: gpio-controller@0 {
113 compatible = "snps,dw-apb-gpio-port";
114 gpio-controller;
115 #gpio-cells = <2>;
118 interrupt-controller;
119 #interrupt-cells = <2>;
120 interrupt-parent = <&intc>;
126 compatible = "snps,dw-apb-gpio";
128 #address-cells = <1>;
129 #size-cells = <0>;
132 clock-names = "bus", "db";
134 port1a: gpio-controller@0 {
135 compatible = "snps,dw-apb-gpio-port";
136 gpio-controller;
137 #gpio-cells = <2>;
140 interrupt-controller;
141 #interrupt-cells = <2>;
142 interrupt-parent = <&intc>;
148 compatible = "snps,dw-apb-gpio";
150 #address-cells = <1>;
151 #size-cells = <0>;
154 clock-names = "bus", "db";
156 port2a: gpio-controller@0 {
157 compatible = "snps,dw-apb-gpio-port";
158 gpio-controller;
159 #gpio-cells = <2>;
162 interrupt-controller;
163 #interrupt-cells = <2>;
164 interrupt-parent = <&intc>;
170 compatible = "sophgo,sg2042-pwm";
172 #pwm-cells = <3>;
174 clock-names = "apb";
178 pllclk: clock-controller@70300100c0 {
179 compatible = "sophgo,sg2042-pll";
182 clock-names = "cgi_main", "cgi_dpll0", "cgi_dpll1";
183 #clock-cells = <1>;
186 msi: msi-controller@7030010304 {
187 compatible = "sophgo,sg2042-msi";
190 reg-names = "clr", "doorbell";
191 msi-controller;
192 #msi-cells = <0>;
193 msi-ranges = <&intc 64 IRQ_TYPE_LEVEL_HIGH 32>;
196 rpgate: clock-controller@7030010368 {
197 compatible = "sophgo,sg2042-rpgate";
200 clock-names = "rpgate";
201 #clock-cells = <1>;
205 compatible = "sophgo,sg2042-pinctrl";
209 clkgen: clock-controller@7030012000 {
210 compatible = "sophgo,sg2042-clkgen";
216 clock-names = "mpll",
220 #clock-cells = <1>;
223 clint_mswi: interrupt-controller@7094000000 {
224 compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi";
226 interrupts-extended = <&cpu0_intc 3>,
293 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
295 reg-names = "mtimecmp";
296 interrupts-extended = <&cpu0_intc 7>,
303 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
305 reg-names = "mtimecmp";
306 interrupts-extended = <&cpu4_intc 7>,
313 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
315 reg-names = "mtimecmp";
316 interrupts-extended = <&cpu8_intc 7>,
323 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
325 reg-names = "mtimecmp";
326 interrupts-extended = <&cpu12_intc 7>,
333 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
335 reg-names = "mtimecmp";
336 interrupts-extended = <&cpu16_intc 7>,
343 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
345 reg-names = "mtimecmp";
346 interrupts-extended = <&cpu20_intc 7>,
353 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
355 reg-names = "mtimecmp";
356 interrupts-extended = <&cpu24_intc 7>,
363 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
365 reg-names = "mtimecmp";
366 interrupts-extended = <&cpu28_intc 7>,
373 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
375 reg-names = "mtimecmp";
376 interrupts-extended = <&cpu32_intc 7>,
383 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
385 reg-names = "mtimecmp";
386 interrupts-extended = <&cpu36_intc 7>,
393 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
395 reg-names = "mtimecmp";
396 interrupts-extended = <&cpu40_intc 7>,
403 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
405 reg-names = "mtimecmp";
406 interrupts-extended = <&cpu44_intc 7>,
413 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
415 reg-names = "mtimecmp";
416 interrupts-extended = <&cpu48_intc 7>,
423 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
425 reg-names = "mtimecmp";
426 interrupts-extended = <&cpu52_intc 7>,
433 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
435 reg-names = "mtimecmp";
436 interrupts-extended = <&cpu56_intc 7>,
443 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
445 reg-names = "mtimecmp";
446 interrupts-extended = <&cpu60_intc 7>,
452 intc: interrupt-controller@7090000000 {
453 compatible = "sophgo,sg2042-plic", "thead,c900-plic";
454 #address-cells = <0>;
455 #interrupt-cells = <2>;
457 interrupt-controller;
458 interrupts-extended =
526 rstgen: reset-controller@7030013000 {
527 compatible = "sophgo,sg2042-reset";
529 #reset-cells = <1>;
533 compatible = "snps,dw-apb-uart";
536 clock-frequency = <500000000>;
539 clock-names = "baudclk", "apb_pclk";
540 reg-shift = <2>;
541 reg-io-width = <4>;
547 compatible = "sophgo,sg2042-spi", "snps,dw-apb-ssi";
550 interrupt-parent = <&intc>;
552 #address-cells = <1>;
553 #size-cells = <0>;
554 num-cs = <2>;
560 compatible = "sophgo,sg2042-spi", "snps,dw-apb-ssi";
563 interrupt-parent = <&intc>;
565 #address-cells = <1>;
566 #size-cells = <0>;
567 num-cs = <2>;
573 compatible = "sophgo,sg2042-dwmac", "snps,dwmac-5.00a";
578 clock-names = "stmmaceth", "ptp_ref", "tx";
579 dma-noncoherent;
580 interrupt-parent = <&intc>;
582 interrupt-names = "macirq";
584 reset-names = "stmmaceth";
585 snps,multicast-filter-bins = <0>;
586 snps,perfect-filter-entries = <1>;
591 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
592 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
593 snps,axi-config = <&gmac0_stmmac_axi_setup>;
597 compatible = "snps,dwmac-mdio";
598 #address-cells = <1>;
599 #size-cells = <0>;
602 gmac0_mtl_rx_setup: rx-queues-config {
603 snps,rx-queues-to-use = <8>;
614 gmac0_mtl_tx_setup: tx-queues-config {
615 snps,tx-queues-to-use = <8>;
626 gmac0_stmmac_axi_setup: stmmac-axi-config {
634 compatible = "sophgo,sg2042-dwcmshc";
636 interrupt-parent = <&intc>;
641 clock-names = "core",
648 compatible = "sophgo,sg2042-dwcmshc";
650 interrupt-parent = <&intc>;
655 clock-names = "core",