Lines Matching +full:interrupt +full:- +full:controller
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #address-cells = <1>;
9 #size-cells = <0>;
10 timebase-frequency = <50000000>;
12 cpu-map {
260 riscv,isa-base = "rv64i";
261 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
267 i-cache-block-size = <64>;
268 i-cache-size = <65536>;
269 i-cache-sets = <512>;
270 d-cache-block-size = <64>;
271 d-cache-size = <65536>;
272 d-cache-sets = <512>;
273 next-level-cache = <&l2_cache0>;
274 mmu-type = "riscv,sv39";
276 cpu0_intc: interrupt-controller {
277 compatible = "riscv,cpu-intc";
278 interrupt-controller;
279 #interrupt-cells = <1>;
287 riscv,isa-base = "rv64i";
288 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
294 i-cache-block-size = <64>;
295 i-cache-size = <65536>;
296 i-cache-sets = <512>;
297 d-cache-block-size = <64>;
298 d-cache-size = <65536>;
299 d-cache-sets = <512>;
300 next-level-cache = <&l2_cache0>;
301 mmu-type = "riscv,sv39";
303 cpu1_intc: interrupt-controller {
304 compatible = "riscv,cpu-intc";
305 interrupt-controller;
306 #interrupt-cells = <1>;
314 riscv,isa-base = "rv64i";
315 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
321 i-cache-block-size = <64>;
322 i-cache-size = <65536>;
323 i-cache-sets = <512>;
324 d-cache-block-size = <64>;
325 d-cache-size = <65536>;
326 d-cache-sets = <512>;
327 next-level-cache = <&l2_cache0>;
328 mmu-type = "riscv,sv39";
330 cpu2_intc: interrupt-controller {
331 compatible = "riscv,cpu-intc";
332 interrupt-controller;
333 #interrupt-cells = <1>;
341 riscv,isa-base = "rv64i";
342 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
348 i-cache-block-size = <64>;
349 i-cache-size = <65536>;
350 i-cache-sets = <512>;
351 d-cache-block-size = <64>;
352 d-cache-size = <65536>;
353 d-cache-sets = <512>;
354 next-level-cache = <&l2_cache0>;
355 mmu-type = "riscv,sv39";
357 cpu3_intc: interrupt-controller {
358 compatible = "riscv,cpu-intc";
359 interrupt-controller;
360 #interrupt-cells = <1>;
368 riscv,isa-base = "rv64i";
369 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
375 i-cache-block-size = <64>;
376 i-cache-size = <65536>;
377 i-cache-sets = <512>;
378 d-cache-block-size = <64>;
379 d-cache-size = <65536>;
380 d-cache-sets = <512>;
381 next-level-cache = <&l2_cache1>;
382 mmu-type = "riscv,sv39";
384 cpu4_intc: interrupt-controller {
385 compatible = "riscv,cpu-intc";
386 interrupt-controller;
387 #interrupt-cells = <1>;
395 riscv,isa-base = "rv64i";
396 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
402 i-cache-block-size = <64>;
403 i-cache-size = <65536>;
404 i-cache-sets = <512>;
405 d-cache-block-size = <64>;
406 d-cache-size = <65536>;
407 d-cache-sets = <512>;
408 next-level-cache = <&l2_cache1>;
409 mmu-type = "riscv,sv39";
411 cpu5_intc: interrupt-controller {
412 compatible = "riscv,cpu-intc";
413 interrupt-controller;
414 #interrupt-cells = <1>;
422 riscv,isa-base = "rv64i";
423 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
429 i-cache-block-size = <64>;
430 i-cache-size = <65536>;
431 i-cache-sets = <512>;
432 d-cache-block-size = <64>;
433 d-cache-size = <65536>;
434 d-cache-sets = <512>;
435 next-level-cache = <&l2_cache1>;
436 mmu-type = "riscv,sv39";
438 cpu6_intc: interrupt-controller {
439 compatible = "riscv,cpu-intc";
440 interrupt-controller;
441 #interrupt-cells = <1>;
449 riscv,isa-base = "rv64i";
450 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
456 i-cache-block-size = <64>;
457 i-cache-size = <65536>;
458 i-cache-sets = <512>;
459 d-cache-block-size = <64>;
460 d-cache-size = <65536>;
461 d-cache-sets = <512>;
462 next-level-cache = <&l2_cache1>;
463 mmu-type = "riscv,sv39";
465 cpu7_intc: interrupt-controller {
466 compatible = "riscv,cpu-intc";
467 interrupt-controller;
468 #interrupt-cells = <1>;
476 riscv,isa-base = "rv64i";
477 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
483 i-cache-block-size = <64>;
484 i-cache-size = <65536>;
485 i-cache-sets = <512>;
486 d-cache-block-size = <64>;
487 d-cache-size = <65536>;
488 d-cache-sets = <512>;
489 next-level-cache = <&l2_cache4>;
490 mmu-type = "riscv,sv39";
492 cpu8_intc: interrupt-controller {
493 compatible = "riscv,cpu-intc";
494 interrupt-controller;
495 #interrupt-cells = <1>;
503 riscv,isa-base = "rv64i";
504 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
510 i-cache-block-size = <64>;
511 i-cache-size = <65536>;
512 i-cache-sets = <512>;
513 d-cache-block-size = <64>;
514 d-cache-size = <65536>;
515 d-cache-sets = <512>;
516 next-level-cache = <&l2_cache4>;
517 mmu-type = "riscv,sv39";
519 cpu9_intc: interrupt-controller {
520 compatible = "riscv,cpu-intc";
521 interrupt-controller;
522 #interrupt-cells = <1>;
530 riscv,isa-base = "rv64i";
531 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
537 i-cache-block-size = <64>;
538 i-cache-size = <65536>;
539 i-cache-sets = <512>;
540 d-cache-block-size = <64>;
541 d-cache-size = <65536>;
542 d-cache-sets = <512>;
543 next-level-cache = <&l2_cache4>;
544 mmu-type = "riscv,sv39";
546 cpu10_intc: interrupt-controller {
547 compatible = "riscv,cpu-intc";
548 interrupt-controller;
549 #interrupt-cells = <1>;
557 riscv,isa-base = "rv64i";
558 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
564 i-cache-block-size = <64>;
565 i-cache-size = <65536>;
566 i-cache-sets = <512>;
567 d-cache-block-size = <64>;
568 d-cache-size = <65536>;
569 d-cache-sets = <512>;
570 next-level-cache = <&l2_cache4>;
571 mmu-type = "riscv,sv39";
573 cpu11_intc: interrupt-controller {
574 compatible = "riscv,cpu-intc";
575 interrupt-controller;
576 #interrupt-cells = <1>;
584 riscv,isa-base = "rv64i";
585 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
591 i-cache-block-size = <64>;
592 i-cache-size = <65536>;
593 i-cache-sets = <512>;
594 d-cache-block-size = <64>;
595 d-cache-size = <65536>;
596 d-cache-sets = <512>;
597 next-level-cache = <&l2_cache5>;
598 mmu-type = "riscv,sv39";
600 cpu12_intc: interrupt-controller {
601 compatible = "riscv,cpu-intc";
602 interrupt-controller;
603 #interrupt-cells = <1>;
611 riscv,isa-base = "rv64i";
612 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
618 i-cache-block-size = <64>;
619 i-cache-size = <65536>;
620 i-cache-sets = <512>;
621 d-cache-block-size = <64>;
622 d-cache-size = <65536>;
623 d-cache-sets = <512>;
624 next-level-cache = <&l2_cache5>;
625 mmu-type = "riscv,sv39";
627 cpu13_intc: interrupt-controller {
628 compatible = "riscv,cpu-intc";
629 interrupt-controller;
630 #interrupt-cells = <1>;
638 riscv,isa-base = "rv64i";
639 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
645 i-cache-block-size = <64>;
646 i-cache-size = <65536>;
647 i-cache-sets = <512>;
648 d-cache-block-size = <64>;
649 d-cache-size = <65536>;
650 d-cache-sets = <512>;
651 next-level-cache = <&l2_cache5>;
652 mmu-type = "riscv,sv39";
654 cpu14_intc: interrupt-controller {
655 compatible = "riscv,cpu-intc";
656 interrupt-controller;
657 #interrupt-cells = <1>;
665 riscv,isa-base = "rv64i";
666 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
672 i-cache-block-size = <64>;
673 i-cache-size = <65536>;
674 i-cache-sets = <512>;
675 d-cache-block-size = <64>;
676 d-cache-size = <65536>;
677 d-cache-sets = <512>;
678 next-level-cache = <&l2_cache5>;
679 mmu-type = "riscv,sv39";
681 cpu15_intc: interrupt-controller {
682 compatible = "riscv,cpu-intc";
683 interrupt-controller;
684 #interrupt-cells = <1>;
692 riscv,isa-base = "rv64i";
693 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
699 i-cache-block-size = <64>;
700 i-cache-size = <65536>;
701 i-cache-sets = <512>;
702 d-cache-block-size = <64>;
703 d-cache-size = <65536>;
704 d-cache-sets = <512>;
705 next-level-cache = <&l2_cache2>;
706 mmu-type = "riscv,sv39";
708 cpu16_intc: interrupt-controller {
709 compatible = "riscv,cpu-intc";
710 interrupt-controller;
711 #interrupt-cells = <1>;
719 riscv,isa-base = "rv64i";
720 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
726 i-cache-block-size = <64>;
727 i-cache-size = <65536>;
728 i-cache-sets = <512>;
729 d-cache-block-size = <64>;
730 d-cache-size = <65536>;
731 d-cache-sets = <512>;
732 next-level-cache = <&l2_cache2>;
733 mmu-type = "riscv,sv39";
735 cpu17_intc: interrupt-controller {
736 compatible = "riscv,cpu-intc";
737 interrupt-controller;
738 #interrupt-cells = <1>;
746 riscv,isa-base = "rv64i";
747 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
753 i-cache-block-size = <64>;
754 i-cache-size = <65536>;
755 i-cache-sets = <512>;
756 d-cache-block-size = <64>;
757 d-cache-size = <65536>;
758 d-cache-sets = <512>;
759 next-level-cache = <&l2_cache2>;
760 mmu-type = "riscv,sv39";
762 cpu18_intc: interrupt-controller {
763 compatible = "riscv,cpu-intc";
764 interrupt-controller;
765 #interrupt-cells = <1>;
773 riscv,isa-base = "rv64i";
774 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
780 i-cache-block-size = <64>;
781 i-cache-size = <65536>;
782 i-cache-sets = <512>;
783 d-cache-block-size = <64>;
784 d-cache-size = <65536>;
785 d-cache-sets = <512>;
786 next-level-cache = <&l2_cache2>;
787 mmu-type = "riscv,sv39";
789 cpu19_intc: interrupt-controller {
790 compatible = "riscv,cpu-intc";
791 interrupt-controller;
792 #interrupt-cells = <1>;
800 riscv,isa-base = "rv64i";
801 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
807 i-cache-block-size = <64>;
808 i-cache-size = <65536>;
809 i-cache-sets = <512>;
810 d-cache-block-size = <64>;
811 d-cache-size = <65536>;
812 d-cache-sets = <512>;
813 next-level-cache = <&l2_cache3>;
814 mmu-type = "riscv,sv39";
816 cpu20_intc: interrupt-controller {
817 compatible = "riscv,cpu-intc";
818 interrupt-controller;
819 #interrupt-cells = <1>;
827 riscv,isa-base = "rv64i";
828 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
834 i-cache-block-size = <64>;
835 i-cache-size = <65536>;
836 i-cache-sets = <512>;
837 d-cache-block-size = <64>;
838 d-cache-size = <65536>;
839 d-cache-sets = <512>;
840 next-level-cache = <&l2_cache3>;
841 mmu-type = "riscv,sv39";
843 cpu21_intc: interrupt-controller {
844 compatible = "riscv,cpu-intc";
845 interrupt-controller;
846 #interrupt-cells = <1>;
854 riscv,isa-base = "rv64i";
855 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
861 i-cache-block-size = <64>;
862 i-cache-size = <65536>;
863 i-cache-sets = <512>;
864 d-cache-block-size = <64>;
865 d-cache-size = <65536>;
866 d-cache-sets = <512>;
867 next-level-cache = <&l2_cache3>;
868 mmu-type = "riscv,sv39";
870 cpu22_intc: interrupt-controller {
871 compatible = "riscv,cpu-intc";
872 interrupt-controller;
873 #interrupt-cells = <1>;
881 riscv,isa-base = "rv64i";
882 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
888 i-cache-block-size = <64>;
889 i-cache-size = <65536>;
890 i-cache-sets = <512>;
891 d-cache-block-size = <64>;
892 d-cache-size = <65536>;
893 d-cache-sets = <512>;
894 next-level-cache = <&l2_cache3>;
895 mmu-type = "riscv,sv39";
897 cpu23_intc: interrupt-controller {
898 compatible = "riscv,cpu-intc";
899 interrupt-controller;
900 #interrupt-cells = <1>;
908 riscv,isa-base = "rv64i";
909 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
915 i-cache-block-size = <64>;
916 i-cache-size = <65536>;
917 i-cache-sets = <512>;
918 d-cache-block-size = <64>;
919 d-cache-size = <65536>;
920 d-cache-sets = <512>;
921 next-level-cache = <&l2_cache6>;
922 mmu-type = "riscv,sv39";
924 cpu24_intc: interrupt-controller {
925 compatible = "riscv,cpu-intc";
926 interrupt-controller;
927 #interrupt-cells = <1>;
935 riscv,isa-base = "rv64i";
936 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
942 i-cache-block-size = <64>;
943 i-cache-size = <65536>;
944 i-cache-sets = <512>;
945 d-cache-block-size = <64>;
946 d-cache-size = <65536>;
947 d-cache-sets = <512>;
948 next-level-cache = <&l2_cache6>;
949 mmu-type = "riscv,sv39";
951 cpu25_intc: interrupt-controller {
952 compatible = "riscv,cpu-intc";
953 interrupt-controller;
954 #interrupt-cells = <1>;
962 riscv,isa-base = "rv64i";
963 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
969 i-cache-block-size = <64>;
970 i-cache-size = <65536>;
971 i-cache-sets = <512>;
972 d-cache-block-size = <64>;
973 d-cache-size = <65536>;
974 d-cache-sets = <512>;
975 next-level-cache = <&l2_cache6>;
976 mmu-type = "riscv,sv39";
978 cpu26_intc: interrupt-controller {
979 compatible = "riscv,cpu-intc";
980 interrupt-controller;
981 #interrupt-cells = <1>;
989 riscv,isa-base = "rv64i";
990 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
996 i-cache-block-size = <64>;
997 i-cache-size = <65536>;
998 i-cache-sets = <512>;
999 d-cache-block-size = <64>;
1000 d-cache-size = <65536>;
1001 d-cache-sets = <512>;
1002 next-level-cache = <&l2_cache6>;
1003 mmu-type = "riscv,sv39";
1005 cpu27_intc: interrupt-controller {
1006 compatible = "riscv,cpu-intc";
1007 interrupt-controller;
1008 #interrupt-cells = <1>;
1016 riscv,isa-base = "rv64i";
1017 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1023 i-cache-block-size = <64>;
1024 i-cache-size = <65536>;
1025 i-cache-sets = <512>;
1026 d-cache-block-size = <64>;
1027 d-cache-size = <65536>;
1028 d-cache-sets = <512>;
1029 next-level-cache = <&l2_cache7>;
1030 mmu-type = "riscv,sv39";
1032 cpu28_intc: interrupt-controller {
1033 compatible = "riscv,cpu-intc";
1034 interrupt-controller;
1035 #interrupt-cells = <1>;
1043 riscv,isa-base = "rv64i";
1044 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1050 i-cache-block-size = <64>;
1051 i-cache-size = <65536>;
1052 i-cache-sets = <512>;
1053 d-cache-block-size = <64>;
1054 d-cache-size = <65536>;
1055 d-cache-sets = <512>;
1056 next-level-cache = <&l2_cache7>;
1057 mmu-type = "riscv,sv39";
1059 cpu29_intc: interrupt-controller {
1060 compatible = "riscv,cpu-intc";
1061 interrupt-controller;
1062 #interrupt-cells = <1>;
1070 riscv,isa-base = "rv64i";
1071 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1077 i-cache-block-size = <64>;
1078 i-cache-size = <65536>;
1079 i-cache-sets = <512>;
1080 d-cache-block-size = <64>;
1081 d-cache-size = <65536>;
1082 d-cache-sets = <512>;
1083 next-level-cache = <&l2_cache7>;
1084 mmu-type = "riscv,sv39";
1086 cpu30_intc: interrupt-controller {
1087 compatible = "riscv,cpu-intc";
1088 interrupt-controller;
1089 #interrupt-cells = <1>;
1097 riscv,isa-base = "rv64i";
1098 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1104 i-cache-block-size = <64>;
1105 i-cache-size = <65536>;
1106 i-cache-sets = <512>;
1107 d-cache-block-size = <64>;
1108 d-cache-size = <65536>;
1109 d-cache-sets = <512>;
1110 next-level-cache = <&l2_cache7>;
1111 mmu-type = "riscv,sv39";
1113 cpu31_intc: interrupt-controller {
1114 compatible = "riscv,cpu-intc";
1115 interrupt-controller;
1116 #interrupt-cells = <1>;
1124 riscv,isa-base = "rv64i";
1125 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1131 i-cache-block-size = <64>;
1132 i-cache-size = <65536>;
1133 i-cache-sets = <512>;
1134 d-cache-block-size = <64>;
1135 d-cache-size = <65536>;
1136 d-cache-sets = <512>;
1137 next-level-cache = <&l2_cache8>;
1138 mmu-type = "riscv,sv39";
1140 cpu32_intc: interrupt-controller {
1141 compatible = "riscv,cpu-intc";
1142 interrupt-controller;
1143 #interrupt-cells = <1>;
1151 riscv,isa-base = "rv64i";
1152 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1158 i-cache-block-size = <64>;
1159 i-cache-size = <65536>;
1160 i-cache-sets = <512>;
1161 d-cache-block-size = <64>;
1162 d-cache-size = <65536>;
1163 d-cache-sets = <512>;
1164 next-level-cache = <&l2_cache8>;
1165 mmu-type = "riscv,sv39";
1167 cpu33_intc: interrupt-controller {
1168 compatible = "riscv,cpu-intc";
1169 interrupt-controller;
1170 #interrupt-cells = <1>;
1178 riscv,isa-base = "rv64i";
1179 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1185 i-cache-block-size = <64>;
1186 i-cache-size = <65536>;
1187 i-cache-sets = <512>;
1188 d-cache-block-size = <64>;
1189 d-cache-size = <65536>;
1190 d-cache-sets = <512>;
1191 next-level-cache = <&l2_cache8>;
1192 mmu-type = "riscv,sv39";
1194 cpu34_intc: interrupt-controller {
1195 compatible = "riscv,cpu-intc";
1196 interrupt-controller;
1197 #interrupt-cells = <1>;
1205 riscv,isa-base = "rv64i";
1206 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1212 i-cache-block-size = <64>;
1213 i-cache-size = <65536>;
1214 i-cache-sets = <512>;
1215 d-cache-block-size = <64>;
1216 d-cache-size = <65536>;
1217 d-cache-sets = <512>;
1218 next-level-cache = <&l2_cache8>;
1219 mmu-type = "riscv,sv39";
1221 cpu35_intc: interrupt-controller {
1222 compatible = "riscv,cpu-intc";
1223 interrupt-controller;
1224 #interrupt-cells = <1>;
1232 riscv,isa-base = "rv64i";
1233 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1239 i-cache-block-size = <64>;
1240 i-cache-size = <65536>;
1241 i-cache-sets = <512>;
1242 d-cache-block-size = <64>;
1243 d-cache-size = <65536>;
1244 d-cache-sets = <512>;
1245 next-level-cache = <&l2_cache9>;
1246 mmu-type = "riscv,sv39";
1248 cpu36_intc: interrupt-controller {
1249 compatible = "riscv,cpu-intc";
1250 interrupt-controller;
1251 #interrupt-cells = <1>;
1259 riscv,isa-base = "rv64i";
1260 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1266 i-cache-block-size = <64>;
1267 i-cache-size = <65536>;
1268 i-cache-sets = <512>;
1269 d-cache-block-size = <64>;
1270 d-cache-size = <65536>;
1271 d-cache-sets = <512>;
1272 next-level-cache = <&l2_cache9>;
1273 mmu-type = "riscv,sv39";
1275 cpu37_intc: interrupt-controller {
1276 compatible = "riscv,cpu-intc";
1277 interrupt-controller;
1278 #interrupt-cells = <1>;
1286 riscv,isa-base = "rv64i";
1287 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1293 i-cache-block-size = <64>;
1294 i-cache-size = <65536>;
1295 i-cache-sets = <512>;
1296 d-cache-block-size = <64>;
1297 d-cache-size = <65536>;
1298 d-cache-sets = <512>;
1299 next-level-cache = <&l2_cache9>;
1300 mmu-type = "riscv,sv39";
1302 cpu38_intc: interrupt-controller {
1303 compatible = "riscv,cpu-intc";
1304 interrupt-controller;
1305 #interrupt-cells = <1>;
1313 riscv,isa-base = "rv64i";
1314 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1320 i-cache-block-size = <64>;
1321 i-cache-size = <65536>;
1322 i-cache-sets = <512>;
1323 d-cache-block-size = <64>;
1324 d-cache-size = <65536>;
1325 d-cache-sets = <512>;
1326 next-level-cache = <&l2_cache9>;
1327 mmu-type = "riscv,sv39";
1329 cpu39_intc: interrupt-controller {
1330 compatible = "riscv,cpu-intc";
1331 interrupt-controller;
1332 #interrupt-cells = <1>;
1340 riscv,isa-base = "rv64i";
1341 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1347 i-cache-block-size = <64>;
1348 i-cache-size = <65536>;
1349 i-cache-sets = <512>;
1350 d-cache-block-size = <64>;
1351 d-cache-size = <65536>;
1352 d-cache-sets = <512>;
1353 next-level-cache = <&l2_cache12>;
1354 mmu-type = "riscv,sv39";
1356 cpu40_intc: interrupt-controller {
1357 compatible = "riscv,cpu-intc";
1358 interrupt-controller;
1359 #interrupt-cells = <1>;
1367 riscv,isa-base = "rv64i";
1368 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1374 i-cache-block-size = <64>;
1375 i-cache-size = <65536>;
1376 i-cache-sets = <512>;
1377 d-cache-block-size = <64>;
1378 d-cache-size = <65536>;
1379 d-cache-sets = <512>;
1380 next-level-cache = <&l2_cache12>;
1381 mmu-type = "riscv,sv39";
1383 cpu41_intc: interrupt-controller {
1384 compatible = "riscv,cpu-intc";
1385 interrupt-controller;
1386 #interrupt-cells = <1>;
1394 riscv,isa-base = "rv64i";
1395 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1401 i-cache-block-size = <64>;
1402 i-cache-size = <65536>;
1403 i-cache-sets = <512>;
1404 d-cache-block-size = <64>;
1405 d-cache-size = <65536>;
1406 d-cache-sets = <512>;
1407 next-level-cache = <&l2_cache12>;
1408 mmu-type = "riscv,sv39";
1410 cpu42_intc: interrupt-controller {
1411 compatible = "riscv,cpu-intc";
1412 interrupt-controller;
1413 #interrupt-cells = <1>;
1421 riscv,isa-base = "rv64i";
1422 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1428 i-cache-block-size = <64>;
1429 i-cache-size = <65536>;
1430 i-cache-sets = <512>;
1431 d-cache-block-size = <64>;
1432 d-cache-size = <65536>;
1433 d-cache-sets = <512>;
1434 next-level-cache = <&l2_cache12>;
1435 mmu-type = "riscv,sv39";
1437 cpu43_intc: interrupt-controller {
1438 compatible = "riscv,cpu-intc";
1439 interrupt-controller;
1440 #interrupt-cells = <1>;
1448 riscv,isa-base = "rv64i";
1449 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1455 i-cache-block-size = <64>;
1456 i-cache-size = <65536>;
1457 i-cache-sets = <512>;
1458 d-cache-block-size = <64>;
1459 d-cache-size = <65536>;
1460 d-cache-sets = <512>;
1461 next-level-cache = <&l2_cache13>;
1462 mmu-type = "riscv,sv39";
1464 cpu44_intc: interrupt-controller {
1465 compatible = "riscv,cpu-intc";
1466 interrupt-controller;
1467 #interrupt-cells = <1>;
1475 riscv,isa-base = "rv64i";
1476 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1482 i-cache-block-size = <64>;
1483 i-cache-size = <65536>;
1484 i-cache-sets = <512>;
1485 d-cache-block-size = <64>;
1486 d-cache-size = <65536>;
1487 d-cache-sets = <512>;
1488 next-level-cache = <&l2_cache13>;
1489 mmu-type = "riscv,sv39";
1491 cpu45_intc: interrupt-controller {
1492 compatible = "riscv,cpu-intc";
1493 interrupt-controller;
1494 #interrupt-cells = <1>;
1502 riscv,isa-base = "rv64i";
1503 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1509 i-cache-block-size = <64>;
1510 i-cache-size = <65536>;
1511 i-cache-sets = <512>;
1512 d-cache-block-size = <64>;
1513 d-cache-size = <65536>;
1514 d-cache-sets = <512>;
1515 next-level-cache = <&l2_cache13>;
1516 mmu-type = "riscv,sv39";
1518 cpu46_intc: interrupt-controller {
1519 compatible = "riscv,cpu-intc";
1520 interrupt-controller;
1521 #interrupt-cells = <1>;
1529 riscv,isa-base = "rv64i";
1530 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1536 i-cache-block-size = <64>;
1537 i-cache-size = <65536>;
1538 i-cache-sets = <512>;
1539 d-cache-block-size = <64>;
1540 d-cache-size = <65536>;
1541 d-cache-sets = <512>;
1542 next-level-cache = <&l2_cache13>;
1543 mmu-type = "riscv,sv39";
1545 cpu47_intc: interrupt-controller {
1546 compatible = "riscv,cpu-intc";
1547 interrupt-controller;
1548 #interrupt-cells = <1>;
1556 riscv,isa-base = "rv64i";
1557 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1563 i-cache-block-size = <64>;
1564 i-cache-size = <65536>;
1565 i-cache-sets = <512>;
1566 d-cache-block-size = <64>;
1567 d-cache-size = <65536>;
1568 d-cache-sets = <512>;
1569 next-level-cache = <&l2_cache10>;
1570 mmu-type = "riscv,sv39";
1572 cpu48_intc: interrupt-controller {
1573 compatible = "riscv,cpu-intc";
1574 interrupt-controller;
1575 #interrupt-cells = <1>;
1583 riscv,isa-base = "rv64i";
1584 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1590 i-cache-block-size = <64>;
1591 i-cache-size = <65536>;
1592 i-cache-sets = <512>;
1593 d-cache-block-size = <64>;
1594 d-cache-size = <65536>;
1595 d-cache-sets = <512>;
1596 next-level-cache = <&l2_cache10>;
1597 mmu-type = "riscv,sv39";
1599 cpu49_intc: interrupt-controller {
1600 compatible = "riscv,cpu-intc";
1601 interrupt-controller;
1602 #interrupt-cells = <1>;
1610 riscv,isa-base = "rv64i";
1611 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1617 i-cache-block-size = <64>;
1618 i-cache-size = <65536>;
1619 i-cache-sets = <512>;
1620 d-cache-block-size = <64>;
1621 d-cache-size = <65536>;
1622 d-cache-sets = <512>;
1623 next-level-cache = <&l2_cache10>;
1624 mmu-type = "riscv,sv39";
1626 cpu50_intc: interrupt-controller {
1627 compatible = "riscv,cpu-intc";
1628 interrupt-controller;
1629 #interrupt-cells = <1>;
1637 riscv,isa-base = "rv64i";
1638 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1644 i-cache-block-size = <64>;
1645 i-cache-size = <65536>;
1646 i-cache-sets = <512>;
1647 d-cache-block-size = <64>;
1648 d-cache-size = <65536>;
1649 d-cache-sets = <512>;
1650 next-level-cache = <&l2_cache10>;
1651 mmu-type = "riscv,sv39";
1653 cpu51_intc: interrupt-controller {
1654 compatible = "riscv,cpu-intc";
1655 interrupt-controller;
1656 #interrupt-cells = <1>;
1664 riscv,isa-base = "rv64i";
1665 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1671 i-cache-block-size = <64>;
1672 i-cache-size = <65536>;
1673 i-cache-sets = <512>;
1674 d-cache-block-size = <64>;
1675 d-cache-size = <65536>;
1676 d-cache-sets = <512>;
1677 next-level-cache = <&l2_cache11>;
1678 mmu-type = "riscv,sv39";
1680 cpu52_intc: interrupt-controller {
1681 compatible = "riscv,cpu-intc";
1682 interrupt-controller;
1683 #interrupt-cells = <1>;
1691 riscv,isa-base = "rv64i";
1692 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1698 i-cache-block-size = <64>;
1699 i-cache-size = <65536>;
1700 i-cache-sets = <512>;
1701 d-cache-block-size = <64>;
1702 d-cache-size = <65536>;
1703 d-cache-sets = <512>;
1704 next-level-cache = <&l2_cache11>;
1705 mmu-type = "riscv,sv39";
1707 cpu53_intc: interrupt-controller {
1708 compatible = "riscv,cpu-intc";
1709 interrupt-controller;
1710 #interrupt-cells = <1>;
1718 riscv,isa-base = "rv64i";
1719 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1725 i-cache-block-size = <64>;
1726 i-cache-size = <65536>;
1727 i-cache-sets = <512>;
1728 d-cache-block-size = <64>;
1729 d-cache-size = <65536>;
1730 d-cache-sets = <512>;
1731 next-level-cache = <&l2_cache11>;
1732 mmu-type = "riscv,sv39";
1734 cpu54_intc: interrupt-controller {
1735 compatible = "riscv,cpu-intc";
1736 interrupt-controller;
1737 #interrupt-cells = <1>;
1745 riscv,isa-base = "rv64i";
1746 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1752 i-cache-block-size = <64>;
1753 i-cache-size = <65536>;
1754 i-cache-sets = <512>;
1755 d-cache-block-size = <64>;
1756 d-cache-size = <65536>;
1757 d-cache-sets = <512>;
1758 next-level-cache = <&l2_cache11>;
1759 mmu-type = "riscv,sv39";
1761 cpu55_intc: interrupt-controller {
1762 compatible = "riscv,cpu-intc";
1763 interrupt-controller;
1764 #interrupt-cells = <1>;
1772 riscv,isa-base = "rv64i";
1773 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1779 i-cache-block-size = <64>;
1780 i-cache-size = <65536>;
1781 i-cache-sets = <512>;
1782 d-cache-block-size = <64>;
1783 d-cache-size = <65536>;
1784 d-cache-sets = <512>;
1785 next-level-cache = <&l2_cache14>;
1786 mmu-type = "riscv,sv39";
1788 cpu56_intc: interrupt-controller {
1789 compatible = "riscv,cpu-intc";
1790 interrupt-controller;
1791 #interrupt-cells = <1>;
1799 riscv,isa-base = "rv64i";
1800 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1806 i-cache-block-size = <64>;
1807 i-cache-size = <65536>;
1808 i-cache-sets = <512>;
1809 d-cache-block-size = <64>;
1810 d-cache-size = <65536>;
1811 d-cache-sets = <512>;
1812 next-level-cache = <&l2_cache14>;
1813 mmu-type = "riscv,sv39";
1815 cpu57_intc: interrupt-controller {
1816 compatible = "riscv,cpu-intc";
1817 interrupt-controller;
1818 #interrupt-cells = <1>;
1826 riscv,isa-base = "rv64i";
1827 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1833 i-cache-block-size = <64>;
1834 i-cache-size = <65536>;
1835 i-cache-sets = <512>;
1836 d-cache-block-size = <64>;
1837 d-cache-size = <65536>;
1838 d-cache-sets = <512>;
1839 next-level-cache = <&l2_cache14>;
1840 mmu-type = "riscv,sv39";
1842 cpu58_intc: interrupt-controller {
1843 compatible = "riscv,cpu-intc";
1844 interrupt-controller;
1845 #interrupt-cells = <1>;
1853 riscv,isa-base = "rv64i";
1854 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1860 i-cache-block-size = <64>;
1861 i-cache-size = <65536>;
1862 i-cache-sets = <512>;
1863 d-cache-block-size = <64>;
1864 d-cache-size = <65536>;
1865 d-cache-sets = <512>;
1866 next-level-cache = <&l2_cache14>;
1867 mmu-type = "riscv,sv39";
1869 cpu59_intc: interrupt-controller {
1870 compatible = "riscv,cpu-intc";
1871 interrupt-controller;
1872 #interrupt-cells = <1>;
1880 riscv,isa-base = "rv64i";
1881 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1887 i-cache-block-size = <64>;
1888 i-cache-size = <65536>;
1889 i-cache-sets = <512>;
1890 d-cache-block-size = <64>;
1891 d-cache-size = <65536>;
1892 d-cache-sets = <512>;
1893 next-level-cache = <&l2_cache15>;
1894 mmu-type = "riscv,sv39";
1896 cpu60_intc: interrupt-controller {
1897 compatible = "riscv,cpu-intc";
1898 interrupt-controller;
1899 #interrupt-cells = <1>;
1907 riscv,isa-base = "rv64i";
1908 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1914 i-cache-block-size = <64>;
1915 i-cache-size = <65536>;
1916 i-cache-sets = <512>;
1917 d-cache-block-size = <64>;
1918 d-cache-size = <65536>;
1919 d-cache-sets = <512>;
1920 next-level-cache = <&l2_cache15>;
1921 mmu-type = "riscv,sv39";
1923 cpu61_intc: interrupt-controller {
1924 compatible = "riscv,cpu-intc";
1925 interrupt-controller;
1926 #interrupt-cells = <1>;
1934 riscv,isa-base = "rv64i";
1935 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1941 i-cache-block-size = <64>;
1942 i-cache-size = <65536>;
1943 i-cache-sets = <512>;
1944 d-cache-block-size = <64>;
1945 d-cache-size = <65536>;
1946 d-cache-sets = <512>;
1947 next-level-cache = <&l2_cache15>;
1948 mmu-type = "riscv,sv39";
1950 cpu62_intc: interrupt-controller {
1951 compatible = "riscv,cpu-intc";
1952 interrupt-controller;
1953 #interrupt-cells = <1>;
1961 riscv,isa-base = "rv64i";
1962 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1968 i-cache-block-size = <64>;
1969 i-cache-size = <65536>;
1970 i-cache-sets = <512>;
1971 d-cache-block-size = <64>;
1972 d-cache-size = <65536>;
1973 d-cache-sets = <512>;
1974 next-level-cache = <&l2_cache15>;
1975 mmu-type = "riscv,sv39";
1977 cpu63_intc: interrupt-controller {
1978 compatible = "riscv,cpu-intc";
1979 interrupt-controller;
1980 #interrupt-cells = <1>;
1984 l2_cache0: cache-controller-0 {
1986 cache-block-size = <64>;
1987 cache-level = <2>;
1988 cache-size = <1048576>;
1989 cache-sets = <1024>;
1990 cache-unified;
1993 l2_cache1: cache-controller-1 {
1995 cache-block-size = <64>;
1996 cache-level = <2>;
1997 cache-size = <1048576>;
1998 cache-sets = <1024>;
1999 cache-unified;
2002 l2_cache2: cache-controller-2 {
2004 cache-block-size = <64>;
2005 cache-level = <2>;
2006 cache-size = <1048576>;
2007 cache-sets = <1024>;
2008 cache-unified;
2011 l2_cache3: cache-controller-3 {
2013 cache-block-size = <64>;
2014 cache-level = <2>;
2015 cache-size = <1048576>;
2016 cache-sets = <1024>;
2017 cache-unified;
2020 l2_cache4: cache-controller-4 {
2022 cache-block-size = <64>;
2023 cache-level = <2>;
2024 cache-size = <1048576>;
2025 cache-sets = <1024>;
2026 cache-unified;
2029 l2_cache5: cache-controller-5 {
2031 cache-block-size = <64>;
2032 cache-level = <2>;
2033 cache-size = <1048576>;
2034 cache-sets = <1024>;
2035 cache-unified;
2038 l2_cache6: cache-controller-6 {
2040 cache-block-size = <64>;
2041 cache-level = <2>;
2042 cache-size = <1048576>;
2043 cache-sets = <1024>;
2044 cache-unified;
2047 l2_cache7: cache-controller-7 {
2049 cache-block-size = <64>;
2050 cache-level = <2>;
2051 cache-size = <1048576>;
2052 cache-sets = <1024>;
2053 cache-unified;
2056 l2_cache8: cache-controller-8 {
2058 cache-block-size = <64>;
2059 cache-level = <2>;
2060 cache-size = <1048576>;
2061 cache-sets = <1024>;
2062 cache-unified;
2065 l2_cache9: cache-controller-9 {
2067 cache-block-size = <64>;
2068 cache-level = <2>;
2069 cache-size = <1048576>;
2070 cache-sets = <1024>;
2071 cache-unified;
2074 l2_cache10: cache-controller-10 {
2076 cache-block-size = <64>;
2077 cache-level = <2>;
2078 cache-size = <1048576>;
2079 cache-sets = <1024>;
2080 cache-unified;
2083 l2_cache11: cache-controller-11 {
2085 cache-block-size = <64>;
2086 cache-level = <2>;
2087 cache-size = <1048576>;
2088 cache-sets = <1024>;
2089 cache-unified;
2092 l2_cache12: cache-controller-12 {
2094 cache-block-size = <64>;
2095 cache-level = <2>;
2096 cache-size = <1048576>;
2097 cache-sets = <1024>;
2098 cache-unified;
2101 l2_cache13: cache-controller-13 {
2103 cache-block-size = <64>;
2104 cache-level = <2>;
2105 cache-size = <1048576>;
2106 cache-sets = <1024>;
2107 cache-unified;
2110 l2_cache14: cache-controller-14 {
2112 cache-block-size = <64>;
2113 cache-level = <2>;
2114 cache-size = <1048576>;
2115 cache-sets = <1024>;
2116 cache-unified;
2119 l2_cache15: cache-controller-15 {
2121 cache-block-size = <64>;
2122 cache-level = <2>;
2123 cache-size = <1048576>;
2124 cache-sets = <1024>;
2125 cache-unified;