Lines Matching +full:1 +full:- +full:cpu
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #address-cells = <1>;
9 #size-cells = <0>;
10 timebase-frequency = <50000000>;
12 cpu-map {
16 cpu = <&cpu0>;
19 cpu = <&cpu1>;
22 cpu = <&cpu2>;
25 cpu = <&cpu3>;
31 cpu = <&cpu4>;
34 cpu = <&cpu5>;
37 cpu = <&cpu6>;
40 cpu = <&cpu7>;
46 cpu = <&cpu16>;
49 cpu = <&cpu17>;
52 cpu = <&cpu18>;
55 cpu = <&cpu19>;
61 cpu = <&cpu20>;
64 cpu = <&cpu21>;
67 cpu = <&cpu22>;
70 cpu = <&cpu23>;
76 cpu = <&cpu8>;
79 cpu = <&cpu9>;
82 cpu = <&cpu10>;
85 cpu = <&cpu11>;
91 cpu = <&cpu12>;
94 cpu = <&cpu13>;
97 cpu = <&cpu14>;
100 cpu = <&cpu15>;
106 cpu = <&cpu24>;
109 cpu = <&cpu25>;
112 cpu = <&cpu26>;
115 cpu = <&cpu27>;
121 cpu = <&cpu28>;
124 cpu = <&cpu29>;
127 cpu = <&cpu30>;
130 cpu = <&cpu31>;
136 cpu = <&cpu32>;
139 cpu = <&cpu33>;
142 cpu = <&cpu34>;
145 cpu = <&cpu35>;
151 cpu = <&cpu36>;
154 cpu = <&cpu37>;
157 cpu = <&cpu38>;
160 cpu = <&cpu39>;
166 cpu = <&cpu48>;
169 cpu = <&cpu49>;
172 cpu = <&cpu50>;
175 cpu = <&cpu51>;
181 cpu = <&cpu52>;
184 cpu = <&cpu53>;
187 cpu = <&cpu54>;
190 cpu = <&cpu55>;
196 cpu = <&cpu40>;
199 cpu = <&cpu41>;
202 cpu = <&cpu42>;
205 cpu = <&cpu43>;
211 cpu = <&cpu44>;
214 cpu = <&cpu45>;
217 cpu = <&cpu46>;
220 cpu = <&cpu47>;
226 cpu = <&cpu56>;
229 cpu = <&cpu57>;
232 cpu = <&cpu58>;
235 cpu = <&cpu59>;
241 cpu = <&cpu60>;
244 cpu = <&cpu61>;
247 cpu = <&cpu62>;
250 cpu = <&cpu63>;
256 cpu0: cpu@0 {
258 device_type = "cpu";
260 riscv,isa-base = "rv64i";
261 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
265 i-cache-block-size = <64>;
266 i-cache-size = <65536>;
267 i-cache-sets = <512>;
268 d-cache-block-size = <64>;
269 d-cache-size = <65536>;
270 d-cache-sets = <512>;
271 next-level-cache = <&l2_cache0>;
272 mmu-type = "riscv,sv39";
274 cpu0_intc: interrupt-controller {
275 compatible = "riscv,cpu-intc";
276 interrupt-controller;
277 #interrupt-cells = <1>;
281 cpu1: cpu@1 {
283 device_type = "cpu";
285 riscv,isa-base = "rv64i";
286 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
289 reg = <1>;
290 i-cache-block-size = <64>;
291 i-cache-size = <65536>;
292 i-cache-sets = <512>;
293 d-cache-block-size = <64>;
294 d-cache-size = <65536>;
295 d-cache-sets = <512>;
296 next-level-cache = <&l2_cache0>;
297 mmu-type = "riscv,sv39";
299 cpu1_intc: interrupt-controller {
300 compatible = "riscv,cpu-intc";
301 interrupt-controller;
302 #interrupt-cells = <1>;
306 cpu2: cpu@2 {
308 device_type = "cpu";
310 riscv,isa-base = "rv64i";
311 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
315 i-cache-block-size = <64>;
316 i-cache-size = <65536>;
317 i-cache-sets = <512>;
318 d-cache-block-size = <64>;
319 d-cache-size = <65536>;
320 d-cache-sets = <512>;
321 next-level-cache = <&l2_cache0>;
322 mmu-type = "riscv,sv39";
324 cpu2_intc: interrupt-controller {
325 compatible = "riscv,cpu-intc";
326 interrupt-controller;
327 #interrupt-cells = <1>;
331 cpu3: cpu@3 {
333 device_type = "cpu";
335 riscv,isa-base = "rv64i";
336 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
340 i-cache-block-size = <64>;
341 i-cache-size = <65536>;
342 i-cache-sets = <512>;
343 d-cache-block-size = <64>;
344 d-cache-size = <65536>;
345 d-cache-sets = <512>;
346 next-level-cache = <&l2_cache0>;
347 mmu-type = "riscv,sv39";
349 cpu3_intc: interrupt-controller {
350 compatible = "riscv,cpu-intc";
351 interrupt-controller;
352 #interrupt-cells = <1>;
356 cpu4: cpu@4 {
358 device_type = "cpu";
360 riscv,isa-base = "rv64i";
361 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
365 i-cache-block-size = <64>;
366 i-cache-size = <65536>;
367 i-cache-sets = <512>;
368 d-cache-block-size = <64>;
369 d-cache-size = <65536>;
370 d-cache-sets = <512>;
371 next-level-cache = <&l2_cache1>;
372 mmu-type = "riscv,sv39";
374 cpu4_intc: interrupt-controller {
375 compatible = "riscv,cpu-intc";
376 interrupt-controller;
377 #interrupt-cells = <1>;
381 cpu5: cpu@5 {
383 device_type = "cpu";
385 riscv,isa-base = "rv64i";
386 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
390 i-cache-block-size = <64>;
391 i-cache-size = <65536>;
392 i-cache-sets = <512>;
393 d-cache-block-size = <64>;
394 d-cache-size = <65536>;
395 d-cache-sets = <512>;
396 next-level-cache = <&l2_cache1>;
397 mmu-type = "riscv,sv39";
399 cpu5_intc: interrupt-controller {
400 compatible = "riscv,cpu-intc";
401 interrupt-controller;
402 #interrupt-cells = <1>;
406 cpu6: cpu@6 {
408 device_type = "cpu";
410 riscv,isa-base = "rv64i";
411 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
415 i-cache-block-size = <64>;
416 i-cache-size = <65536>;
417 i-cache-sets = <512>;
418 d-cache-block-size = <64>;
419 d-cache-size = <65536>;
420 d-cache-sets = <512>;
421 next-level-cache = <&l2_cache1>;
422 mmu-type = "riscv,sv39";
424 cpu6_intc: interrupt-controller {
425 compatible = "riscv,cpu-intc";
426 interrupt-controller;
427 #interrupt-cells = <1>;
431 cpu7: cpu@7 {
433 device_type = "cpu";
435 riscv,isa-base = "rv64i";
436 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
440 i-cache-block-size = <64>;
441 i-cache-size = <65536>;
442 i-cache-sets = <512>;
443 d-cache-block-size = <64>;
444 d-cache-size = <65536>;
445 d-cache-sets = <512>;
446 next-level-cache = <&l2_cache1>;
447 mmu-type = "riscv,sv39";
449 cpu7_intc: interrupt-controller {
450 compatible = "riscv,cpu-intc";
451 interrupt-controller;
452 #interrupt-cells = <1>;
456 cpu8: cpu@8 {
458 device_type = "cpu";
460 riscv,isa-base = "rv64i";
461 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
465 i-cache-block-size = <64>;
466 i-cache-size = <65536>;
467 i-cache-sets = <512>;
468 d-cache-block-size = <64>;
469 d-cache-size = <65536>;
470 d-cache-sets = <512>;
471 next-level-cache = <&l2_cache4>;
472 mmu-type = "riscv,sv39";
474 cpu8_intc: interrupt-controller {
475 compatible = "riscv,cpu-intc";
476 interrupt-controller;
477 #interrupt-cells = <1>;
481 cpu9: cpu@9 {
483 device_type = "cpu";
485 riscv,isa-base = "rv64i";
486 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
490 i-cache-block-size = <64>;
491 i-cache-size = <65536>;
492 i-cache-sets = <512>;
493 d-cache-block-size = <64>;
494 d-cache-size = <65536>;
495 d-cache-sets = <512>;
496 next-level-cache = <&l2_cache4>;
497 mmu-type = "riscv,sv39";
499 cpu9_intc: interrupt-controller {
500 compatible = "riscv,cpu-intc";
501 interrupt-controller;
502 #interrupt-cells = <1>;
506 cpu10: cpu@10 {
508 device_type = "cpu";
510 riscv,isa-base = "rv64i";
511 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
515 i-cache-block-size = <64>;
516 i-cache-size = <65536>;
517 i-cache-sets = <512>;
518 d-cache-block-size = <64>;
519 d-cache-size = <65536>;
520 d-cache-sets = <512>;
521 next-level-cache = <&l2_cache4>;
522 mmu-type = "riscv,sv39";
524 cpu10_intc: interrupt-controller {
525 compatible = "riscv,cpu-intc";
526 interrupt-controller;
527 #interrupt-cells = <1>;
531 cpu11: cpu@11 {
533 device_type = "cpu";
535 riscv,isa-base = "rv64i";
536 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
540 i-cache-block-size = <64>;
541 i-cache-size = <65536>;
542 i-cache-sets = <512>;
543 d-cache-block-size = <64>;
544 d-cache-size = <65536>;
545 d-cache-sets = <512>;
546 next-level-cache = <&l2_cache4>;
547 mmu-type = "riscv,sv39";
549 cpu11_intc: interrupt-controller {
550 compatible = "riscv,cpu-intc";
551 interrupt-controller;
552 #interrupt-cells = <1>;
556 cpu12: cpu@12 {
558 device_type = "cpu";
560 riscv,isa-base = "rv64i";
561 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
565 i-cache-block-size = <64>;
566 i-cache-size = <65536>;
567 i-cache-sets = <512>;
568 d-cache-block-size = <64>;
569 d-cache-size = <65536>;
570 d-cache-sets = <512>;
571 next-level-cache = <&l2_cache5>;
572 mmu-type = "riscv,sv39";
574 cpu12_intc: interrupt-controller {
575 compatible = "riscv,cpu-intc";
576 interrupt-controller;
577 #interrupt-cells = <1>;
581 cpu13: cpu@13 {
583 device_type = "cpu";
585 riscv,isa-base = "rv64i";
586 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
590 i-cache-block-size = <64>;
591 i-cache-size = <65536>;
592 i-cache-sets = <512>;
593 d-cache-block-size = <64>;
594 d-cache-size = <65536>;
595 d-cache-sets = <512>;
596 next-level-cache = <&l2_cache5>;
597 mmu-type = "riscv,sv39";
599 cpu13_intc: interrupt-controller {
600 compatible = "riscv,cpu-intc";
601 interrupt-controller;
602 #interrupt-cells = <1>;
606 cpu14: cpu@14 {
608 device_type = "cpu";
610 riscv,isa-base = "rv64i";
611 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
615 i-cache-block-size = <64>;
616 i-cache-size = <65536>;
617 i-cache-sets = <512>;
618 d-cache-block-size = <64>;
619 d-cache-size = <65536>;
620 d-cache-sets = <512>;
621 next-level-cache = <&l2_cache5>;
622 mmu-type = "riscv,sv39";
624 cpu14_intc: interrupt-controller {
625 compatible = "riscv,cpu-intc";
626 interrupt-controller;
627 #interrupt-cells = <1>;
631 cpu15: cpu@15 {
633 device_type = "cpu";
635 riscv,isa-base = "rv64i";
636 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
640 i-cache-block-size = <64>;
641 i-cache-size = <65536>;
642 i-cache-sets = <512>;
643 d-cache-block-size = <64>;
644 d-cache-size = <65536>;
645 d-cache-sets = <512>;
646 next-level-cache = <&l2_cache5>;
647 mmu-type = "riscv,sv39";
649 cpu15_intc: interrupt-controller {
650 compatible = "riscv,cpu-intc";
651 interrupt-controller;
652 #interrupt-cells = <1>;
656 cpu16: cpu@16 {
658 device_type = "cpu";
660 riscv,isa-base = "rv64i";
661 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
665 i-cache-block-size = <64>;
666 i-cache-size = <65536>;
667 i-cache-sets = <512>;
668 d-cache-block-size = <64>;
669 d-cache-size = <65536>;
670 d-cache-sets = <512>;
671 next-level-cache = <&l2_cache2>;
672 mmu-type = "riscv,sv39";
674 cpu16_intc: interrupt-controller {
675 compatible = "riscv,cpu-intc";
676 interrupt-controller;
677 #interrupt-cells = <1>;
681 cpu17: cpu@17 {
683 device_type = "cpu";
685 riscv,isa-base = "rv64i";
686 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
690 i-cache-block-size = <64>;
691 i-cache-size = <65536>;
692 i-cache-sets = <512>;
693 d-cache-block-size = <64>;
694 d-cache-size = <65536>;
695 d-cache-sets = <512>;
696 next-level-cache = <&l2_cache2>;
697 mmu-type = "riscv,sv39";
699 cpu17_intc: interrupt-controller {
700 compatible = "riscv,cpu-intc";
701 interrupt-controller;
702 #interrupt-cells = <1>;
706 cpu18: cpu@18 {
708 device_type = "cpu";
710 riscv,isa-base = "rv64i";
711 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
715 i-cache-block-size = <64>;
716 i-cache-size = <65536>;
717 i-cache-sets = <512>;
718 d-cache-block-size = <64>;
719 d-cache-size = <65536>;
720 d-cache-sets = <512>;
721 next-level-cache = <&l2_cache2>;
722 mmu-type = "riscv,sv39";
724 cpu18_intc: interrupt-controller {
725 compatible = "riscv,cpu-intc";
726 interrupt-controller;
727 #interrupt-cells = <1>;
731 cpu19: cpu@19 {
733 device_type = "cpu";
735 riscv,isa-base = "rv64i";
736 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
740 i-cache-block-size = <64>;
741 i-cache-size = <65536>;
742 i-cache-sets = <512>;
743 d-cache-block-size = <64>;
744 d-cache-size = <65536>;
745 d-cache-sets = <512>;
746 next-level-cache = <&l2_cache2>;
747 mmu-type = "riscv,sv39";
749 cpu19_intc: interrupt-controller {
750 compatible = "riscv,cpu-intc";
751 interrupt-controller;
752 #interrupt-cells = <1>;
756 cpu20: cpu@20 {
758 device_type = "cpu";
760 riscv,isa-base = "rv64i";
761 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
765 i-cache-block-size = <64>;
766 i-cache-size = <65536>;
767 i-cache-sets = <512>;
768 d-cache-block-size = <64>;
769 d-cache-size = <65536>;
770 d-cache-sets = <512>;
771 next-level-cache = <&l2_cache3>;
772 mmu-type = "riscv,sv39";
774 cpu20_intc: interrupt-controller {
775 compatible = "riscv,cpu-intc";
776 interrupt-controller;
777 #interrupt-cells = <1>;
781 cpu21: cpu@21 {
783 device_type = "cpu";
785 riscv,isa-base = "rv64i";
786 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
790 i-cache-block-size = <64>;
791 i-cache-size = <65536>;
792 i-cache-sets = <512>;
793 d-cache-block-size = <64>;
794 d-cache-size = <65536>;
795 d-cache-sets = <512>;
796 next-level-cache = <&l2_cache3>;
797 mmu-type = "riscv,sv39";
799 cpu21_intc: interrupt-controller {
800 compatible = "riscv,cpu-intc";
801 interrupt-controller;
802 #interrupt-cells = <1>;
806 cpu22: cpu@22 {
808 device_type = "cpu";
810 riscv,isa-base = "rv64i";
811 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
815 i-cache-block-size = <64>;
816 i-cache-size = <65536>;
817 i-cache-sets = <512>;
818 d-cache-block-size = <64>;
819 d-cache-size = <65536>;
820 d-cache-sets = <512>;
821 next-level-cache = <&l2_cache3>;
822 mmu-type = "riscv,sv39";
824 cpu22_intc: interrupt-controller {
825 compatible = "riscv,cpu-intc";
826 interrupt-controller;
827 #interrupt-cells = <1>;
831 cpu23: cpu@23 {
833 device_type = "cpu";
835 riscv,isa-base = "rv64i";
836 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
840 i-cache-block-size = <64>;
841 i-cache-size = <65536>;
842 i-cache-sets = <512>;
843 d-cache-block-size = <64>;
844 d-cache-size = <65536>;
845 d-cache-sets = <512>;
846 next-level-cache = <&l2_cache3>;
847 mmu-type = "riscv,sv39";
849 cpu23_intc: interrupt-controller {
850 compatible = "riscv,cpu-intc";
851 interrupt-controller;
852 #interrupt-cells = <1>;
856 cpu24: cpu@24 {
858 device_type = "cpu";
860 riscv,isa-base = "rv64i";
861 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
865 i-cache-block-size = <64>;
866 i-cache-size = <65536>;
867 i-cache-sets = <512>;
868 d-cache-block-size = <64>;
869 d-cache-size = <65536>;
870 d-cache-sets = <512>;
871 next-level-cache = <&l2_cache6>;
872 mmu-type = "riscv,sv39";
874 cpu24_intc: interrupt-controller {
875 compatible = "riscv,cpu-intc";
876 interrupt-controller;
877 #interrupt-cells = <1>;
881 cpu25: cpu@25 {
883 device_type = "cpu";
885 riscv,isa-base = "rv64i";
886 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
890 i-cache-block-size = <64>;
891 i-cache-size = <65536>;
892 i-cache-sets = <512>;
893 d-cache-block-size = <64>;
894 d-cache-size = <65536>;
895 d-cache-sets = <512>;
896 next-level-cache = <&l2_cache6>;
897 mmu-type = "riscv,sv39";
899 cpu25_intc: interrupt-controller {
900 compatible = "riscv,cpu-intc";
901 interrupt-controller;
902 #interrupt-cells = <1>;
906 cpu26: cpu@26 {
908 device_type = "cpu";
910 riscv,isa-base = "rv64i";
911 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
915 i-cache-block-size = <64>;
916 i-cache-size = <65536>;
917 i-cache-sets = <512>;
918 d-cache-block-size = <64>;
919 d-cache-size = <65536>;
920 d-cache-sets = <512>;
921 next-level-cache = <&l2_cache6>;
922 mmu-type = "riscv,sv39";
924 cpu26_intc: interrupt-controller {
925 compatible = "riscv,cpu-intc";
926 interrupt-controller;
927 #interrupt-cells = <1>;
931 cpu27: cpu@27 {
933 device_type = "cpu";
935 riscv,isa-base = "rv64i";
936 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
940 i-cache-block-size = <64>;
941 i-cache-size = <65536>;
942 i-cache-sets = <512>;
943 d-cache-block-size = <64>;
944 d-cache-size = <65536>;
945 d-cache-sets = <512>;
946 next-level-cache = <&l2_cache6>;
947 mmu-type = "riscv,sv39";
949 cpu27_intc: interrupt-controller {
950 compatible = "riscv,cpu-intc";
951 interrupt-controller;
952 #interrupt-cells = <1>;
956 cpu28: cpu@28 {
958 device_type = "cpu";
960 riscv,isa-base = "rv64i";
961 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
965 i-cache-block-size = <64>;
966 i-cache-size = <65536>;
967 i-cache-sets = <512>;
968 d-cache-block-size = <64>;
969 d-cache-size = <65536>;
970 d-cache-sets = <512>;
971 next-level-cache = <&l2_cache7>;
972 mmu-type = "riscv,sv39";
974 cpu28_intc: interrupt-controller {
975 compatible = "riscv,cpu-intc";
976 interrupt-controller;
977 #interrupt-cells = <1>;
981 cpu29: cpu@29 {
983 device_type = "cpu";
985 riscv,isa-base = "rv64i";
986 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
990 i-cache-block-size = <64>;
991 i-cache-size = <65536>;
992 i-cache-sets = <512>;
993 d-cache-block-size = <64>;
994 d-cache-size = <65536>;
995 d-cache-sets = <512>;
996 next-level-cache = <&l2_cache7>;
997 mmu-type = "riscv,sv39";
999 cpu29_intc: interrupt-controller {
1000 compatible = "riscv,cpu-intc";
1001 interrupt-controller;
1002 #interrupt-cells = <1>;
1006 cpu30: cpu@30 {
1008 device_type = "cpu";
1010 riscv,isa-base = "rv64i";
1011 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1015 i-cache-block-size = <64>;
1016 i-cache-size = <65536>;
1017 i-cache-sets = <512>;
1018 d-cache-block-size = <64>;
1019 d-cache-size = <65536>;
1020 d-cache-sets = <512>;
1021 next-level-cache = <&l2_cache7>;
1022 mmu-type = "riscv,sv39";
1024 cpu30_intc: interrupt-controller {
1025 compatible = "riscv,cpu-intc";
1026 interrupt-controller;
1027 #interrupt-cells = <1>;
1031 cpu31: cpu@31 {
1033 device_type = "cpu";
1035 riscv,isa-base = "rv64i";
1036 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1040 i-cache-block-size = <64>;
1041 i-cache-size = <65536>;
1042 i-cache-sets = <512>;
1043 d-cache-block-size = <64>;
1044 d-cache-size = <65536>;
1045 d-cache-sets = <512>;
1046 next-level-cache = <&l2_cache7>;
1047 mmu-type = "riscv,sv39";
1049 cpu31_intc: interrupt-controller {
1050 compatible = "riscv,cpu-intc";
1051 interrupt-controller;
1052 #interrupt-cells = <1>;
1056 cpu32: cpu@32 {
1058 device_type = "cpu";
1060 riscv,isa-base = "rv64i";
1061 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1065 i-cache-block-size = <64>;
1066 i-cache-size = <65536>;
1067 i-cache-sets = <512>;
1068 d-cache-block-size = <64>;
1069 d-cache-size = <65536>;
1070 d-cache-sets = <512>;
1071 next-level-cache = <&l2_cache8>;
1072 mmu-type = "riscv,sv39";
1074 cpu32_intc: interrupt-controller {
1075 compatible = "riscv,cpu-intc";
1076 interrupt-controller;
1077 #interrupt-cells = <1>;
1081 cpu33: cpu@33 {
1083 device_type = "cpu";
1085 riscv,isa-base = "rv64i";
1086 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1090 i-cache-block-size = <64>;
1091 i-cache-size = <65536>;
1092 i-cache-sets = <512>;
1093 d-cache-block-size = <64>;
1094 d-cache-size = <65536>;
1095 d-cache-sets = <512>;
1096 next-level-cache = <&l2_cache8>;
1097 mmu-type = "riscv,sv39";
1099 cpu33_intc: interrupt-controller {
1100 compatible = "riscv,cpu-intc";
1101 interrupt-controller;
1102 #interrupt-cells = <1>;
1106 cpu34: cpu@34 {
1108 device_type = "cpu";
1110 riscv,isa-base = "rv64i";
1111 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1115 i-cache-block-size = <64>;
1116 i-cache-size = <65536>;
1117 i-cache-sets = <512>;
1118 d-cache-block-size = <64>;
1119 d-cache-size = <65536>;
1120 d-cache-sets = <512>;
1121 next-level-cache = <&l2_cache8>;
1122 mmu-type = "riscv,sv39";
1124 cpu34_intc: interrupt-controller {
1125 compatible = "riscv,cpu-intc";
1126 interrupt-controller;
1127 #interrupt-cells = <1>;
1131 cpu35: cpu@35 {
1133 device_type = "cpu";
1135 riscv,isa-base = "rv64i";
1136 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1140 i-cache-block-size = <64>;
1141 i-cache-size = <65536>;
1142 i-cache-sets = <512>;
1143 d-cache-block-size = <64>;
1144 d-cache-size = <65536>;
1145 d-cache-sets = <512>;
1146 next-level-cache = <&l2_cache8>;
1147 mmu-type = "riscv,sv39";
1149 cpu35_intc: interrupt-controller {
1150 compatible = "riscv,cpu-intc";
1151 interrupt-controller;
1152 #interrupt-cells = <1>;
1156 cpu36: cpu@36 {
1158 device_type = "cpu";
1160 riscv,isa-base = "rv64i";
1161 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1165 i-cache-block-size = <64>;
1166 i-cache-size = <65536>;
1167 i-cache-sets = <512>;
1168 d-cache-block-size = <64>;
1169 d-cache-size = <65536>;
1170 d-cache-sets = <512>;
1171 next-level-cache = <&l2_cache9>;
1172 mmu-type = "riscv,sv39";
1174 cpu36_intc: interrupt-controller {
1175 compatible = "riscv,cpu-intc";
1176 interrupt-controller;
1177 #interrupt-cells = <1>;
1181 cpu37: cpu@37 {
1183 device_type = "cpu";
1185 riscv,isa-base = "rv64i";
1186 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1190 i-cache-block-size = <64>;
1191 i-cache-size = <65536>;
1192 i-cache-sets = <512>;
1193 d-cache-block-size = <64>;
1194 d-cache-size = <65536>;
1195 d-cache-sets = <512>;
1196 next-level-cache = <&l2_cache9>;
1197 mmu-type = "riscv,sv39";
1199 cpu37_intc: interrupt-controller {
1200 compatible = "riscv,cpu-intc";
1201 interrupt-controller;
1202 #interrupt-cells = <1>;
1206 cpu38: cpu@38 {
1208 device_type = "cpu";
1210 riscv,isa-base = "rv64i";
1211 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1215 i-cache-block-size = <64>;
1216 i-cache-size = <65536>;
1217 i-cache-sets = <512>;
1218 d-cache-block-size = <64>;
1219 d-cache-size = <65536>;
1220 d-cache-sets = <512>;
1221 next-level-cache = <&l2_cache9>;
1222 mmu-type = "riscv,sv39";
1224 cpu38_intc: interrupt-controller {
1225 compatible = "riscv,cpu-intc";
1226 interrupt-controller;
1227 #interrupt-cells = <1>;
1231 cpu39: cpu@39 {
1233 device_type = "cpu";
1235 riscv,isa-base = "rv64i";
1236 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1240 i-cache-block-size = <64>;
1241 i-cache-size = <65536>;
1242 i-cache-sets = <512>;
1243 d-cache-block-size = <64>;
1244 d-cache-size = <65536>;
1245 d-cache-sets = <512>;
1246 next-level-cache = <&l2_cache9>;
1247 mmu-type = "riscv,sv39";
1249 cpu39_intc: interrupt-controller {
1250 compatible = "riscv,cpu-intc";
1251 interrupt-controller;
1252 #interrupt-cells = <1>;
1256 cpu40: cpu@40 {
1258 device_type = "cpu";
1260 riscv,isa-base = "rv64i";
1261 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1265 i-cache-block-size = <64>;
1266 i-cache-size = <65536>;
1267 i-cache-sets = <512>;
1268 d-cache-block-size = <64>;
1269 d-cache-size = <65536>;
1270 d-cache-sets = <512>;
1271 next-level-cache = <&l2_cache12>;
1272 mmu-type = "riscv,sv39";
1274 cpu40_intc: interrupt-controller {
1275 compatible = "riscv,cpu-intc";
1276 interrupt-controller;
1277 #interrupt-cells = <1>;
1281 cpu41: cpu@41 {
1283 device_type = "cpu";
1285 riscv,isa-base = "rv64i";
1286 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1290 i-cache-block-size = <64>;
1291 i-cache-size = <65536>;
1292 i-cache-sets = <512>;
1293 d-cache-block-size = <64>;
1294 d-cache-size = <65536>;
1295 d-cache-sets = <512>;
1296 next-level-cache = <&l2_cache12>;
1297 mmu-type = "riscv,sv39";
1299 cpu41_intc: interrupt-controller {
1300 compatible = "riscv,cpu-intc";
1301 interrupt-controller;
1302 #interrupt-cells = <1>;
1306 cpu42: cpu@42 {
1308 device_type = "cpu";
1310 riscv,isa-base = "rv64i";
1311 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1315 i-cache-block-size = <64>;
1316 i-cache-size = <65536>;
1317 i-cache-sets = <512>;
1318 d-cache-block-size = <64>;
1319 d-cache-size = <65536>;
1320 d-cache-sets = <512>;
1321 next-level-cache = <&l2_cache12>;
1322 mmu-type = "riscv,sv39";
1324 cpu42_intc: interrupt-controller {
1325 compatible = "riscv,cpu-intc";
1326 interrupt-controller;
1327 #interrupt-cells = <1>;
1331 cpu43: cpu@43 {
1333 device_type = "cpu";
1335 riscv,isa-base = "rv64i";
1336 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1340 i-cache-block-size = <64>;
1341 i-cache-size = <65536>;
1342 i-cache-sets = <512>;
1343 d-cache-block-size = <64>;
1344 d-cache-size = <65536>;
1345 d-cache-sets = <512>;
1346 next-level-cache = <&l2_cache12>;
1347 mmu-type = "riscv,sv39";
1349 cpu43_intc: interrupt-controller {
1350 compatible = "riscv,cpu-intc";
1351 interrupt-controller;
1352 #interrupt-cells = <1>;
1356 cpu44: cpu@44 {
1358 device_type = "cpu";
1360 riscv,isa-base = "rv64i";
1361 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1365 i-cache-block-size = <64>;
1366 i-cache-size = <65536>;
1367 i-cache-sets = <512>;
1368 d-cache-block-size = <64>;
1369 d-cache-size = <65536>;
1370 d-cache-sets = <512>;
1371 next-level-cache = <&l2_cache13>;
1372 mmu-type = "riscv,sv39";
1374 cpu44_intc: interrupt-controller {
1375 compatible = "riscv,cpu-intc";
1376 interrupt-controller;
1377 #interrupt-cells = <1>;
1381 cpu45: cpu@45 {
1383 device_type = "cpu";
1385 riscv,isa-base = "rv64i";
1386 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1390 i-cache-block-size = <64>;
1391 i-cache-size = <65536>;
1392 i-cache-sets = <512>;
1393 d-cache-block-size = <64>;
1394 d-cache-size = <65536>;
1395 d-cache-sets = <512>;
1396 next-level-cache = <&l2_cache13>;
1397 mmu-type = "riscv,sv39";
1399 cpu45_intc: interrupt-controller {
1400 compatible = "riscv,cpu-intc";
1401 interrupt-controller;
1402 #interrupt-cells = <1>;
1406 cpu46: cpu@46 {
1408 device_type = "cpu";
1410 riscv,isa-base = "rv64i";
1411 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1415 i-cache-block-size = <64>;
1416 i-cache-size = <65536>;
1417 i-cache-sets = <512>;
1418 d-cache-block-size = <64>;
1419 d-cache-size = <65536>;
1420 d-cache-sets = <512>;
1421 next-level-cache = <&l2_cache13>;
1422 mmu-type = "riscv,sv39";
1424 cpu46_intc: interrupt-controller {
1425 compatible = "riscv,cpu-intc";
1426 interrupt-controller;
1427 #interrupt-cells = <1>;
1431 cpu47: cpu@47 {
1433 device_type = "cpu";
1435 riscv,isa-base = "rv64i";
1436 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1440 i-cache-block-size = <64>;
1441 i-cache-size = <65536>;
1442 i-cache-sets = <512>;
1443 d-cache-block-size = <64>;
1444 d-cache-size = <65536>;
1445 d-cache-sets = <512>;
1446 next-level-cache = <&l2_cache13>;
1447 mmu-type = "riscv,sv39";
1449 cpu47_intc: interrupt-controller {
1450 compatible = "riscv,cpu-intc";
1451 interrupt-controller;
1452 #interrupt-cells = <1>;
1456 cpu48: cpu@48 {
1458 device_type = "cpu";
1460 riscv,isa-base = "rv64i";
1461 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1465 i-cache-block-size = <64>;
1466 i-cache-size = <65536>;
1467 i-cache-sets = <512>;
1468 d-cache-block-size = <64>;
1469 d-cache-size = <65536>;
1470 d-cache-sets = <512>;
1471 next-level-cache = <&l2_cache10>;
1472 mmu-type = "riscv,sv39";
1474 cpu48_intc: interrupt-controller {
1475 compatible = "riscv,cpu-intc";
1476 interrupt-controller;
1477 #interrupt-cells = <1>;
1481 cpu49: cpu@49 {
1483 device_type = "cpu";
1485 riscv,isa-base = "rv64i";
1486 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1490 i-cache-block-size = <64>;
1491 i-cache-size = <65536>;
1492 i-cache-sets = <512>;
1493 d-cache-block-size = <64>;
1494 d-cache-size = <65536>;
1495 d-cache-sets = <512>;
1496 next-level-cache = <&l2_cache10>;
1497 mmu-type = "riscv,sv39";
1499 cpu49_intc: interrupt-controller {
1500 compatible = "riscv,cpu-intc";
1501 interrupt-controller;
1502 #interrupt-cells = <1>;
1506 cpu50: cpu@50 {
1508 device_type = "cpu";
1510 riscv,isa-base = "rv64i";
1511 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1515 i-cache-block-size = <64>;
1516 i-cache-size = <65536>;
1517 i-cache-sets = <512>;
1518 d-cache-block-size = <64>;
1519 d-cache-size = <65536>;
1520 d-cache-sets = <512>;
1521 next-level-cache = <&l2_cache10>;
1522 mmu-type = "riscv,sv39";
1524 cpu50_intc: interrupt-controller {
1525 compatible = "riscv,cpu-intc";
1526 interrupt-controller;
1527 #interrupt-cells = <1>;
1531 cpu51: cpu@51 {
1533 device_type = "cpu";
1535 riscv,isa-base = "rv64i";
1536 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1540 i-cache-block-size = <64>;
1541 i-cache-size = <65536>;
1542 i-cache-sets = <512>;
1543 d-cache-block-size = <64>;
1544 d-cache-size = <65536>;
1545 d-cache-sets = <512>;
1546 next-level-cache = <&l2_cache10>;
1547 mmu-type = "riscv,sv39";
1549 cpu51_intc: interrupt-controller {
1550 compatible = "riscv,cpu-intc";
1551 interrupt-controller;
1552 #interrupt-cells = <1>;
1556 cpu52: cpu@52 {
1558 device_type = "cpu";
1560 riscv,isa-base = "rv64i";
1561 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1565 i-cache-block-size = <64>;
1566 i-cache-size = <65536>;
1567 i-cache-sets = <512>;
1568 d-cache-block-size = <64>;
1569 d-cache-size = <65536>;
1570 d-cache-sets = <512>;
1571 next-level-cache = <&l2_cache11>;
1572 mmu-type = "riscv,sv39";
1574 cpu52_intc: interrupt-controller {
1575 compatible = "riscv,cpu-intc";
1576 interrupt-controller;
1577 #interrupt-cells = <1>;
1581 cpu53: cpu@53 {
1583 device_type = "cpu";
1585 riscv,isa-base = "rv64i";
1586 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1590 i-cache-block-size = <64>;
1591 i-cache-size = <65536>;
1592 i-cache-sets = <512>;
1593 d-cache-block-size = <64>;
1594 d-cache-size = <65536>;
1595 d-cache-sets = <512>;
1596 next-level-cache = <&l2_cache11>;
1597 mmu-type = "riscv,sv39";
1599 cpu53_intc: interrupt-controller {
1600 compatible = "riscv,cpu-intc";
1601 interrupt-controller;
1602 #interrupt-cells = <1>;
1606 cpu54: cpu@54 {
1608 device_type = "cpu";
1610 riscv,isa-base = "rv64i";
1611 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1615 i-cache-block-size = <64>;
1616 i-cache-size = <65536>;
1617 i-cache-sets = <512>;
1618 d-cache-block-size = <64>;
1619 d-cache-size = <65536>;
1620 d-cache-sets = <512>;
1621 next-level-cache = <&l2_cache11>;
1622 mmu-type = "riscv,sv39";
1624 cpu54_intc: interrupt-controller {
1625 compatible = "riscv,cpu-intc";
1626 interrupt-controller;
1627 #interrupt-cells = <1>;
1631 cpu55: cpu@55 {
1633 device_type = "cpu";
1635 riscv,isa-base = "rv64i";
1636 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1640 i-cache-block-size = <64>;
1641 i-cache-size = <65536>;
1642 i-cache-sets = <512>;
1643 d-cache-block-size = <64>;
1644 d-cache-size = <65536>;
1645 d-cache-sets = <512>;
1646 next-level-cache = <&l2_cache11>;
1647 mmu-type = "riscv,sv39";
1649 cpu55_intc: interrupt-controller {
1650 compatible = "riscv,cpu-intc";
1651 interrupt-controller;
1652 #interrupt-cells = <1>;
1656 cpu56: cpu@56 {
1658 device_type = "cpu";
1660 riscv,isa-base = "rv64i";
1661 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1665 i-cache-block-size = <64>;
1666 i-cache-size = <65536>;
1667 i-cache-sets = <512>;
1668 d-cache-block-size = <64>;
1669 d-cache-size = <65536>;
1670 d-cache-sets = <512>;
1671 next-level-cache = <&l2_cache14>;
1672 mmu-type = "riscv,sv39";
1674 cpu56_intc: interrupt-controller {
1675 compatible = "riscv,cpu-intc";
1676 interrupt-controller;
1677 #interrupt-cells = <1>;
1681 cpu57: cpu@57 {
1683 device_type = "cpu";
1685 riscv,isa-base = "rv64i";
1686 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1690 i-cache-block-size = <64>;
1691 i-cache-size = <65536>;
1692 i-cache-sets = <512>;
1693 d-cache-block-size = <64>;
1694 d-cache-size = <65536>;
1695 d-cache-sets = <512>;
1696 next-level-cache = <&l2_cache14>;
1697 mmu-type = "riscv,sv39";
1699 cpu57_intc: interrupt-controller {
1700 compatible = "riscv,cpu-intc";
1701 interrupt-controller;
1702 #interrupt-cells = <1>;
1706 cpu58: cpu@58 {
1708 device_type = "cpu";
1710 riscv,isa-base = "rv64i";
1711 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1715 i-cache-block-size = <64>;
1716 i-cache-size = <65536>;
1717 i-cache-sets = <512>;
1718 d-cache-block-size = <64>;
1719 d-cache-size = <65536>;
1720 d-cache-sets = <512>;
1721 next-level-cache = <&l2_cache14>;
1722 mmu-type = "riscv,sv39";
1724 cpu58_intc: interrupt-controller {
1725 compatible = "riscv,cpu-intc";
1726 interrupt-controller;
1727 #interrupt-cells = <1>;
1731 cpu59: cpu@59 {
1733 device_type = "cpu";
1735 riscv,isa-base = "rv64i";
1736 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1740 i-cache-block-size = <64>;
1741 i-cache-size = <65536>;
1742 i-cache-sets = <512>;
1743 d-cache-block-size = <64>;
1744 d-cache-size = <65536>;
1745 d-cache-sets = <512>;
1746 next-level-cache = <&l2_cache14>;
1747 mmu-type = "riscv,sv39";
1749 cpu59_intc: interrupt-controller {
1750 compatible = "riscv,cpu-intc";
1751 interrupt-controller;
1752 #interrupt-cells = <1>;
1756 cpu60: cpu@60 {
1758 device_type = "cpu";
1760 riscv,isa-base = "rv64i";
1761 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1765 i-cache-block-size = <64>;
1766 i-cache-size = <65536>;
1767 i-cache-sets = <512>;
1768 d-cache-block-size = <64>;
1769 d-cache-size = <65536>;
1770 d-cache-sets = <512>;
1771 next-level-cache = <&l2_cache15>;
1772 mmu-type = "riscv,sv39";
1774 cpu60_intc: interrupt-controller {
1775 compatible = "riscv,cpu-intc";
1776 interrupt-controller;
1777 #interrupt-cells = <1>;
1781 cpu61: cpu@61 {
1783 device_type = "cpu";
1785 riscv,isa-base = "rv64i";
1786 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1790 i-cache-block-size = <64>;
1791 i-cache-size = <65536>;
1792 i-cache-sets = <512>;
1793 d-cache-block-size = <64>;
1794 d-cache-size = <65536>;
1795 d-cache-sets = <512>;
1796 next-level-cache = <&l2_cache15>;
1797 mmu-type = "riscv,sv39";
1799 cpu61_intc: interrupt-controller {
1800 compatible = "riscv,cpu-intc";
1801 interrupt-controller;
1802 #interrupt-cells = <1>;
1806 cpu62: cpu@62 {
1808 device_type = "cpu";
1810 riscv,isa-base = "rv64i";
1811 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1815 i-cache-block-size = <64>;
1816 i-cache-size = <65536>;
1817 i-cache-sets = <512>;
1818 d-cache-block-size = <64>;
1819 d-cache-size = <65536>;
1820 d-cache-sets = <512>;
1821 next-level-cache = <&l2_cache15>;
1822 mmu-type = "riscv,sv39";
1824 cpu62_intc: interrupt-controller {
1825 compatible = "riscv,cpu-intc";
1826 interrupt-controller;
1827 #interrupt-cells = <1>;
1831 cpu63: cpu@63 {
1833 device_type = "cpu";
1835 riscv,isa-base = "rv64i";
1836 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
1840 i-cache-block-size = <64>;
1841 i-cache-size = <65536>;
1842 i-cache-sets = <512>;
1843 d-cache-block-size = <64>;
1844 d-cache-size = <65536>;
1845 d-cache-sets = <512>;
1846 next-level-cache = <&l2_cache15>;
1847 mmu-type = "riscv,sv39";
1849 cpu63_intc: interrupt-controller {
1850 compatible = "riscv,cpu-intc";
1851 interrupt-controller;
1852 #interrupt-cells = <1>;
1856 l2_cache0: cache-controller-0 {
1858 cache-block-size = <64>;
1859 cache-level = <2>;
1860 cache-size = <1048576>;
1861 cache-sets = <1024>;
1862 cache-unified;
1865 l2_cache1: cache-controller-1 {
1867 cache-block-size = <64>;
1868 cache-level = <2>;
1869 cache-size = <1048576>;
1870 cache-sets = <1024>;
1871 cache-unified;
1874 l2_cache2: cache-controller-2 {
1876 cache-block-size = <64>;
1877 cache-level = <2>;
1878 cache-size = <1048576>;
1879 cache-sets = <1024>;
1880 cache-unified;
1883 l2_cache3: cache-controller-3 {
1885 cache-block-size = <64>;
1886 cache-level = <2>;
1887 cache-size = <1048576>;
1888 cache-sets = <1024>;
1889 cache-unified;
1892 l2_cache4: cache-controller-4 {
1894 cache-block-size = <64>;
1895 cache-level = <2>;
1896 cache-size = <1048576>;
1897 cache-sets = <1024>;
1898 cache-unified;
1901 l2_cache5: cache-controller-5 {
1903 cache-block-size = <64>;
1904 cache-level = <2>;
1905 cache-size = <1048576>;
1906 cache-sets = <1024>;
1907 cache-unified;
1910 l2_cache6: cache-controller-6 {
1912 cache-block-size = <64>;
1913 cache-level = <2>;
1914 cache-size = <1048576>;
1915 cache-sets = <1024>;
1916 cache-unified;
1919 l2_cache7: cache-controller-7 {
1921 cache-block-size = <64>;
1922 cache-level = <2>;
1923 cache-size = <1048576>;
1924 cache-sets = <1024>;
1925 cache-unified;
1928 l2_cache8: cache-controller-8 {
1930 cache-block-size = <64>;
1931 cache-level = <2>;
1932 cache-size = <1048576>;
1933 cache-sets = <1024>;
1934 cache-unified;
1937 l2_cache9: cache-controller-9 {
1939 cache-block-size = <64>;
1940 cache-level = <2>;
1941 cache-size = <1048576>;
1942 cache-sets = <1024>;
1943 cache-unified;
1946 l2_cache10: cache-controller-10 {
1948 cache-block-size = <64>;
1949 cache-level = <2>;
1950 cache-size = <1048576>;
1951 cache-sets = <1024>;
1952 cache-unified;
1955 l2_cache11: cache-controller-11 {
1957 cache-block-size = <64>;
1958 cache-level = <2>;
1959 cache-size = <1048576>;
1960 cache-sets = <1024>;
1961 cache-unified;
1964 l2_cache12: cache-controller-12 {
1966 cache-block-size = <64>;
1967 cache-level = <2>;
1968 cache-size = <1048576>;
1969 cache-sets = <1024>;
1970 cache-unified;
1973 l2_cache13: cache-controller-13 {
1975 cache-block-size = <64>;
1976 cache-level = <2>;
1977 cache-size = <1048576>;
1978 cache-sets = <1024>;
1979 cache-unified;
1982 l2_cache14: cache-controller-14 {
1984 cache-block-size = <64>;
1985 cache-level = <2>;
1986 cache-size = <1048576>;
1987 cache-sets = <1024>;
1988 cache-unified;
1991 l2_cache15: cache-controller-15 {
1993 cache-block-size = <64>;
1994 cache-level = <2>;
1995 cache-size = <1048576>;
1996 cache-sets = <1024>;
1997 cache-unified;