Lines Matching +full:reg +full:- +full:io +full:- +full:width
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/clock/sophgo,cv1800.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
18 timebase-frequency = <25000000>;
23 reg = <0>;
24 d-cache-block-size = <64>;
25 d-cache-sets = <512>;
26 d-cache-size = <65536>;
27 i-cache-block-size = <64>;
28 i-cache-sets = <128>;
29 i-cache-size = <32768>;
30 mmu-type = "riscv,sv39";
32 riscv,isa-base = "rv64i";
33 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
36 cpu0_intc: interrupt-controller {
37 compatible = "riscv,cpu-intc";
38 interrupt-controller;
39 #interrupt-cells = <1>;
45 compatible = "fixed-clock";
46 clock-output-names = "osc_25m";
47 #clock-cells = <0>;
51 compatible = "simple-bus";
52 interrupt-parent = <&plic>;
53 #address-cells = <1>;
54 #size-cells = <1>;
55 dma-noncoherent;
58 clk: clock-controller@3002000 {
59 reg = <0x03002000 0x1000>;
61 #clock-cells = <1>;
65 compatible = "snps,dw-apb-gpio";
66 reg = <0x3020000 0x1000>;
67 #address-cells = <1>;
68 #size-cells = <0>;
70 porta: gpio-controller@0 {
71 compatible = "snps,dw-apb-gpio-port";
72 gpio-controller;
73 #gpio-cells = <2>;
75 reg = <0>;
76 interrupt-controller;
77 #interrupt-cells = <2>;
83 compatible = "snps,dw-apb-gpio";
84 reg = <0x3021000 0x1000>;
85 #address-cells = <1>;
86 #size-cells = <0>;
88 portb: gpio-controller@0 {
89 compatible = "snps,dw-apb-gpio-port";
90 gpio-controller;
91 #gpio-cells = <2>;
93 reg = <0>;
94 interrupt-controller;
95 #interrupt-cells = <2>;
101 compatible = "snps,dw-apb-gpio";
102 reg = <0x3022000 0x1000>;
103 #address-cells = <1>;
104 #size-cells = <0>;
106 portc: gpio-controller@0 {
107 compatible = "snps,dw-apb-gpio-port";
108 gpio-controller;
109 #gpio-cells = <2>;
111 reg = <0>;
112 interrupt-controller;
113 #interrupt-cells = <2>;
119 compatible = "snps,dw-apb-gpio";
120 reg = <0x3023000 0x1000>;
121 #address-cells = <1>;
122 #size-cells = <0>;
124 portd: gpio-controller@0 {
125 compatible = "snps,dw-apb-gpio-port";
126 gpio-controller;
127 #gpio-cells = <2>;
129 reg = <0>;
130 interrupt-controller;
131 #interrupt-cells = <2>;
137 compatible = "snps,designware-i2c";
138 reg = <0x04000000 0x10000>;
139 #address-cells = <1>;
140 #size-cells = <0>;
142 clock-names = "ref", "pclk";
148 compatible = "snps,designware-i2c";
149 reg = <0x04010000 0x10000>;
150 #address-cells = <1>;
151 #size-cells = <0>;
153 clock-names = "ref", "pclk";
159 compatible = "snps,designware-i2c";
160 reg = <0x04020000 0x10000>;
161 #address-cells = <1>;
162 #size-cells = <0>;
164 clock-names = "ref", "pclk";
170 compatible = "snps,designware-i2c";
171 reg = <0x04030000 0x10000>;
172 #address-cells = <1>;
173 #size-cells = <0>;
175 clock-names = "ref", "pclk";
181 compatible = "snps,designware-i2c";
182 reg = <0x04040000 0x10000>;
183 #address-cells = <1>;
184 #size-cells = <0>;
186 clock-names = "ref", "pclk";
192 compatible = "snps,dw-apb-uart";
193 reg = <0x04140000 0x100>;
196 clock-names = "baudclk", "apb_pclk";
197 reg-shift = <2>;
198 reg-io-width = <4>;
203 compatible = "snps,dw-apb-uart";
204 reg = <0x04150000 0x100>;
207 clock-names = "baudclk", "apb_pclk";
208 reg-shift = <2>;
209 reg-io-width = <4>;
214 compatible = "snps,dw-apb-uart";
215 reg = <0x04160000 0x100>;
218 clock-names = "baudclk", "apb_pclk";
219 reg-shift = <2>;
220 reg-io-width = <4>;
225 compatible = "snps,dw-apb-uart";
226 reg = <0x04170000 0x100>;
229 clock-names = "baudclk", "apb_pclk";
230 reg-shift = <2>;
231 reg-io-width = <4>;
236 compatible = "snps,dw-apb-ssi";
237 reg = <0x04180000 0x10000>;
238 #address-cells = <1>;
239 #size-cells = <0>;
241 clock-names = "ssi_clk", "pclk";
247 compatible = "snps,dw-apb-ssi";
248 reg = <0x04190000 0x10000>;
249 #address-cells = <1>;
250 #size-cells = <0>;
252 clock-names = "ssi_clk", "pclk";
258 compatible = "snps,dw-apb-ssi";
259 reg = <0x041a0000 0x10000>;
260 #address-cells = <1>;
261 #size-cells = <0>;
263 clock-names = "ssi_clk", "pclk";
269 compatible = "snps,dw-apb-ssi";
270 reg = <0x041b0000 0x10000>;
271 #address-cells = <1>;
272 #size-cells = <0>;
274 clock-names = "ssi_clk", "pclk";
280 compatible = "snps,dw-apb-uart";
281 reg = <0x041c0000 0x100>;
284 clock-names = "baudclk", "apb_pclk";
285 reg-shift = <2>;
286 reg-io-width = <4>;
291 compatible = "sophgo,cv1800b-dwcmshc";
292 reg = <0x4310000 0x1000>;
296 clock-names = "core", "bus";
300 dmac: dma-controller@4330000 {
301 compatible = "snps,axi-dma-1.01a";
302 reg = <0x04330000 0x1000>;
305 clock-names = "core-clk", "cfgr-clk";
306 #dma-cells = <1>;
307 dma-channels = <8>;
308 snps,block-size = <1024 1024 1024 1024
311 snps,dma-masters = <2>;
312 snps,data-width = <4>;
316 plic: interrupt-controller@70000000 {
317 reg = <0x70000000 0x4000000>;
318 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
319 interrupt-controller;
320 #address-cells = <0>;
321 #interrupt-cells = <2>;
326 reg = <0x74000000 0x10000>;
327 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;