Lines Matching +full:dw +full:- +full:apb +full:- +full:gpio
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/clock/sophgo,cv1800.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
18 timebase-frequency = <25000000>;
24 d-cache-block-size = <64>;
25 d-cache-sets = <512>;
26 d-cache-size = <65536>;
27 i-cache-block-size = <64>;
28 i-cache-sets = <128>;
29 i-cache-size = <32768>;
30 mmu-type = "riscv,sv39";
32 riscv,isa-base = "rv64i";
33 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
36 cpu0_intc: interrupt-controller {
37 compatible = "riscv,cpu-intc";
38 interrupt-controller;
39 #interrupt-cells = <1>;
45 compatible = "fixed-clock";
46 clock-output-names = "osc_25m";
47 #clock-cells = <0>;
51 compatible = "simple-bus";
52 interrupt-parent = <&plic>;
53 #address-cells = <1>;
54 #size-cells = <1>;
55 dma-noncoherent;
58 clk: clock-controller@3002000 {
61 #clock-cells = <1>;
64 gpio0: gpio@3020000 {
65 compatible = "snps,dw-apb-gpio";
67 #address-cells = <1>;
68 #size-cells = <0>;
70 porta: gpio-controller@0 {
71 compatible = "snps,dw-apb-gpio-port";
72 gpio-controller;
73 #gpio-cells = <2>;
76 interrupt-controller;
77 #interrupt-cells = <2>;
82 gpio1: gpio@3021000 {
83 compatible = "snps,dw-apb-gpio";
85 #address-cells = <1>;
86 #size-cells = <0>;
88 portb: gpio-controller@0 {
89 compatible = "snps,dw-apb-gpio-port";
90 gpio-controller;
91 #gpio-cells = <2>;
94 interrupt-controller;
95 #interrupt-cells = <2>;
100 gpio2: gpio@3022000 {
101 compatible = "snps,dw-apb-gpio";
103 #address-cells = <1>;
104 #size-cells = <0>;
106 portc: gpio-controller@0 {
107 compatible = "snps,dw-apb-gpio-port";
108 gpio-controller;
109 #gpio-cells = <2>;
112 interrupt-controller;
113 #interrupt-cells = <2>;
118 gpio3: gpio@3023000 {
119 compatible = "snps,dw-apb-gpio";
121 #address-cells = <1>;
122 #size-cells = <0>;
124 portd: gpio-controller@0 {
125 compatible = "snps,dw-apb-gpio-port";
126 gpio-controller;
127 #gpio-cells = <2>;
130 interrupt-controller;
131 #interrupt-cells = <2>;
137 compatible = "sophgo,cv1800b-saradc";
141 #address-cells = <1>;
142 #size-cells = <0>;
159 compatible = "snps,designware-i2c";
161 #address-cells = <1>;
162 #size-cells = <0>;
164 clock-names = "ref", "pclk";
170 compatible = "snps,designware-i2c";
172 #address-cells = <1>;
173 #size-cells = <0>;
175 clock-names = "ref", "pclk";
181 compatible = "snps,designware-i2c";
183 #address-cells = <1>;
184 #size-cells = <0>;
186 clock-names = "ref", "pclk";
192 compatible = "snps,designware-i2c";
194 #address-cells = <1>;
195 #size-cells = <0>;
197 clock-names = "ref", "pclk";
203 compatible = "snps,designware-i2c";
205 #address-cells = <1>;
206 #size-cells = <0>;
208 clock-names = "ref", "pclk";
214 compatible = "snps,dw-apb-uart";
218 clock-names = "baudclk", "apb_pclk";
219 reg-shift = <2>;
220 reg-io-width = <4>;
225 compatible = "snps,dw-apb-uart";
229 clock-names = "baudclk", "apb_pclk";
230 reg-shift = <2>;
231 reg-io-width = <4>;
236 compatible = "snps,dw-apb-uart";
240 clock-names = "baudclk", "apb_pclk";
241 reg-shift = <2>;
242 reg-io-width = <4>;
247 compatible = "snps,dw-apb-uart";
251 clock-names = "baudclk", "apb_pclk";
252 reg-shift = <2>;
253 reg-io-width = <4>;
258 compatible = "snps,dw-apb-ssi";
260 #address-cells = <1>;
261 #size-cells = <0>;
263 clock-names = "ssi_clk", "pclk";
269 compatible = "snps,dw-apb-ssi";
271 #address-cells = <1>;
272 #size-cells = <0>;
274 clock-names = "ssi_clk", "pclk";
280 compatible = "snps,dw-apb-ssi";
282 #address-cells = <1>;
283 #size-cells = <0>;
285 clock-names = "ssi_clk", "pclk";
291 compatible = "snps,dw-apb-ssi";
293 #address-cells = <1>;
294 #size-cells = <0>;
296 clock-names = "ssi_clk", "pclk";
302 compatible = "snps,dw-apb-uart";
306 clock-names = "baudclk", "apb_pclk";
307 reg-shift = <2>;
308 reg-io-width = <4>;
313 compatible = "sophgo,cv1800b-dwcmshc";
318 clock-names = "core", "bus";
323 compatible = "sophgo,cv1800b-dwcmshc";
328 clock-names = "core", "bus";
332 dmac: dma-controller@4330000 {
333 compatible = "snps,axi-dma-1.01a";
337 clock-names = "core-clk", "cfgr-clk";
338 #dma-cells = <1>;
339 dma-channels = <8>;
340 snps,block-size = <1024 1024 1024 1024
343 snps,dma-masters = <2>;
344 snps,data-width = <4>;
348 plic: interrupt-controller@70000000 {
350 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
351 interrupt-controller;
352 #address-cells = <0>;
353 #interrupt-cells = <2>;
359 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;