Lines Matching +full:cache +full:- +full:controller +full:- +full:0
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu740-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu740-c000", "sifive,fu740";
23 #address-cells = <1>;
24 #size-cells = <0>;
25 cpu0: cpu@0 {
28 i-cache-block-size = <64>;
29 i-cache-sets = <128>;
30 i-cache-size = <16384>;
31 next-level-cache = <&ccache>;
32 reg = <0x0>;
34 riscv,isa-base = "rv64i";
35 riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
38 cpu0_intc: interrupt-controller {
39 #interrupt-cells = <1>;
40 compatible = "riscv,cpu-intc";
41 interrupt-controller;
46 d-cache-block-size = <64>;
47 d-cache-sets = <64>;
48 d-cache-size = <32768>;
49 d-tlb-sets = <1>;
50 d-tlb-size = <40>;
52 i-cache-block-size = <64>;
53 i-cache-sets = <128>;
54 i-cache-size = <32768>;
55 i-tlb-sets = <1>;
56 i-tlb-size = <40>;
57 mmu-type = "riscv,sv39";
58 next-level-cache = <&ccache>;
59 reg = <0x1>;
61 riscv,isa-base = "rv64i";
62 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
64 tlb-split;
65 cpu1_intc: interrupt-controller {
66 #interrupt-cells = <1>;
67 compatible = "riscv,cpu-intc";
68 interrupt-controller;
73 d-cache-block-size = <64>;
74 d-cache-sets = <64>;
75 d-cache-size = <32768>;
76 d-tlb-sets = <1>;
77 d-tlb-size = <40>;
79 i-cache-block-size = <64>;
80 i-cache-sets = <128>;
81 i-cache-size = <32768>;
82 i-tlb-sets = <1>;
83 i-tlb-size = <40>;
84 mmu-type = "riscv,sv39";
85 next-level-cache = <&ccache>;
86 reg = <0x2>;
88 riscv,isa-base = "rv64i";
89 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
91 tlb-split;
92 cpu2_intc: interrupt-controller {
93 #interrupt-cells = <1>;
94 compatible = "riscv,cpu-intc";
95 interrupt-controller;
100 d-cache-block-size = <64>;
101 d-cache-sets = <64>;
102 d-cache-size = <32768>;
103 d-tlb-sets = <1>;
104 d-tlb-size = <40>;
106 i-cache-block-size = <64>;
107 i-cache-sets = <128>;
108 i-cache-size = <32768>;
109 i-tlb-sets = <1>;
110 i-tlb-size = <40>;
111 mmu-type = "riscv,sv39";
112 next-level-cache = <&ccache>;
113 reg = <0x3>;
115 riscv,isa-base = "rv64i";
116 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
118 tlb-split;
119 cpu3_intc: interrupt-controller {
120 #interrupt-cells = <1>;
121 compatible = "riscv,cpu-intc";
122 interrupt-controller;
127 d-cache-block-size = <64>;
128 d-cache-sets = <64>;
129 d-cache-size = <32768>;
130 d-tlb-sets = <1>;
131 d-tlb-size = <40>;
133 i-cache-block-size = <64>;
134 i-cache-sets = <128>;
135 i-cache-size = <32768>;
136 i-tlb-sets = <1>;
137 i-tlb-size = <40>;
138 mmu-type = "riscv,sv39";
139 next-level-cache = <&ccache>;
140 reg = <0x4>;
142 riscv,isa-base = "rv64i";
143 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
145 tlb-split;
146 cpu4_intc: interrupt-controller {
147 #interrupt-cells = <1>;
148 compatible = "riscv,cpu-intc";
149 interrupt-controller;
153 cpu-map {
178 #address-cells = <2>;
179 #size-cells = <2>;
180 compatible = "simple-bus";
182 plic0: interrupt-controller@c000000 {
183 #interrupt-cells = <1>;
184 #address-cells = <0>;
185 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
186 reg = <0x0 0xc000000 0x0 0x4000000>;
188 interrupt-controller;
189 interrupts-extended =
190 <&cpu0_intc 0xffffffff>,
191 <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>,
192 <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>,
193 <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>,
194 <&cpu4_intc 0xffffffff>, <&cpu4_intc 9>;
196 prci: clock-controller@10000000 {
197 compatible = "sifive,fu740-c000-prci";
198 reg = <0x0 0x10000000 0x0 0x1000>;
200 #clock-cells = <1>;
201 #reset-cells = <1>;
204 compatible = "sifive,fu740-c000-uart", "sifive,uart0";
205 reg = <0x0 0x10010000 0x0 0x1000>;
206 interrupt-parent = <&plic0>;
212 compatible = "sifive,fu740-c000-uart", "sifive,uart0";
213 reg = <0x0 0x10011000 0x0 0x1000>;
214 interrupt-parent = <&plic0>;
220 compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";
221 reg = <0x0 0x10030000 0x0 0x1000>;
222 interrupt-parent = <&plic0>;
225 reg-shift = <2>;
226 reg-io-width = <1>;
227 #address-cells = <1>;
228 #size-cells = <0>;
232 compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";
233 reg = <0x0 0x10031000 0x0 0x1000>;
234 interrupt-parent = <&plic0>;
237 reg-shift = <2>;
238 reg-io-width = <1>;
239 #address-cells = <1>;
240 #size-cells = <0>;
244 compatible = "sifive,fu740-c000-spi", "sifive,spi0";
245 reg = <0x0 0x10040000 0x0 0x1000>,
246 <0x0 0x20000000 0x0 0x10000000>;
247 interrupt-parent = <&plic0>;
250 #address-cells = <1>;
251 #size-cells = <0>;
255 compatible = "sifive,fu740-c000-spi", "sifive,spi0";
256 reg = <0x0 0x10041000 0x0 0x1000>,
257 <0x0 0x30000000 0x0 0x10000000>;
258 interrupt-parent = <&plic0>;
261 #address-cells = <1>;
262 #size-cells = <0>;
266 compatible = "sifive,fu740-c000-spi", "sifive,spi0";
267 reg = <0x0 0x10050000 0x0 0x1000>;
268 interrupt-parent = <&plic0>;
271 #address-cells = <1>;
272 #size-cells = <0>;
276 compatible = "sifive,fu540-c000-gem";
277 interrupt-parent = <&plic0>;
279 reg = <0x0 0x10090000 0x0 0x2000>,
280 <0x0 0x100a0000 0x0 0x1000>;
281 local-mac-address = [00 00 00 00 00 00];
282 clock-names = "pclk", "hclk";
285 #address-cells = <1>;
286 #size-cells = <0>;
290 compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
291 reg = <0x0 0x10020000 0x0 0x1000>;
292 interrupt-parent = <&plic0>;
295 #pwm-cells = <3>;
299 compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
300 reg = <0x0 0x10021000 0x0 0x1000>;
301 interrupt-parent = <&plic0>;
304 #pwm-cells = <3>;
307 ccache: cache-controller@2010000 {
308 compatible = "sifive,fu740-c000-ccache", "cache";
309 cache-block-size = <64>;
310 cache-level = <2>;
311 cache-sets = <2048>;
312 cache-size = <2097152>;
313 cache-unified;
314 interrupt-parent = <&plic0>;
316 reg = <0x0 0x2010000 0x0 0x1000>;
319 compatible = "sifive,fu740-c000-gpio", "sifive,gpio0";
320 interrupt-parent = <&plic0>;
324 reg = <0x0 0x10060000 0x0 0x1000>;
325 gpio-controller;
326 #gpio-cells = <2>;
327 interrupt-controller;
328 #interrupt-cells = <2>;
333 compatible = "sifive,fu740-pcie";
334 #address-cells = <3>;
335 #size-cells = <2>;
336 #interrupt-cells = <1>;
337 reg = <0xe 0x00000000 0x0 0x80000000>,
338 <0xd 0xf0000000 0x0 0x10000000>,
339 <0x0 0x100d0000 0x0 0x1000>;
340 reg-names = "dbi", "config", "mgmt";
342 dma-coherent;
343 bus-range = <0x0 0xff>;
344 ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000>, /* I/O */
345 <0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000>, /* mem */
346 <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x10000000>, /* mem */
347 <0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; /* mem prefetchable */
348 num-lanes = <0x8>;
350 interrupt-names = "msi", "inta", "intb", "intc", "intd";
351 interrupt-parent = <&plic0>;
352 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
353 interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>,
354 <0x0 0x0 0x0 0x2 &plic0 58>,
355 <0x0 0x0 0x0 0x3 &plic0 59>,
356 <0x0 0x0 0x0 0x4 &plic0 60>;
357 clock-names = "pcie_aux";
359 pwren-gpios = <&gpio 5 0>;
360 reset-gpios = <&gpio 8 0>;