Lines Matching +full:isa +full:- +full:extensions

1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/irq.h>
16 		#address-cells = <1>;
17 		#size-cells = <0>;
18 		timebase-frequency = <12000000>;
23 			#cooling-cells = <2>;
26 			riscv,isa = "rv64imafdc";
27 			riscv,isa-base = "rv64i";
28 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
31 			mmu-type = "riscv,sv39";
32 			i-cache-size = <0x8000>;
33 			i-cache-line-size = <0x40>;
34 			d-cache-size = <0x8000>;
35 			d-cache-line-size = <0x40>;
36 			next-level-cache = <&l2cache>;
38 			operating-points-v2 = <&cluster0_opp>;
40 			cpu0_intc: interrupt-controller {
41 				#interrupt-cells = <1>;
42 				compatible = "andestech,cpu-intc", "riscv,cpu-intc";
43 				interrupt-controller;
50 	gpio-ranges = <&pinctrl 0 0 232>;
54 	dma-noncoherent;
55 	interrupt-parent = <&plic>;
57 	irqc: interrupt-controller@110a0000 {
58 		compatible = "renesas,r9a07g043f-irqc";
60 		#interrupt-cells = <2>;
61 		#address-cells = <0>;
62 		interrupt-controller;
111 		interrupt-names = "nmi",
122 				  "bus-err", "ec7tie1-0", "ec7tie2-0",
123 				  "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1",
124 				  "ec7tiovf-1";
127 		clock-names = "clk", "pclk";
128 		power-domains = <&cpg>;
132 	plic: interrupt-controller@12c00000 {
133 		compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
134 		#interrupt-cells = <2>;
135 		#address-cells = <0>;
137 		interrupt-controller;
140 		power-domains = <&cpg>;
142 		interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
145 	l2cache: cache-controller@13400000 {
146 		compatible = "andestech,ax45mp-cache", "cache";
149 		cache-size = <0x40000>;
150 		cache-line-size = <64>;
151 		cache-sets = <1024>;
152 		cache-unified;
153 		cache-level = <2>;