Lines Matching +full:mpfs +full:- +full:ccc
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
8 #address-cells = <2>;
9 #size-cells = <2>;
11 compatible = "microchip,mpfs";
14 #address-cells = <1>;
15 #size-cells = <0>;
16 timebase-frequency = <1000000>;
21 i-cache-block-size = <64>;
22 i-cache-sets = <128>;
23 i-cache-size = <16384>;
26 riscv,isa-base = "rv64i";
27 riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
32 cpu0_intc: interrupt-controller {
33 #interrupt-cells = <1>;
34 compatible = "riscv,cpu-intc";
35 interrupt-controller;
40 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
41 d-cache-block-size = <64>;
42 d-cache-sets = <64>;
43 d-cache-size = <32768>;
44 d-tlb-sets = <1>;
45 d-tlb-size = <32>;
47 i-cache-block-size = <64>;
48 i-cache-sets = <64>;
49 i-cache-size = <32768>;
50 i-tlb-sets = <1>;
51 i-tlb-size = <32>;
52 mmu-type = "riscv,sv39";
55 riscv,isa-base = "rv64i";
56 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
59 tlb-split;
60 next-level-cache = <&cctrllr>;
63 cpu1_intc: interrupt-controller {
64 #interrupt-cells = <1>;
65 compatible = "riscv,cpu-intc";
66 interrupt-controller;
71 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
72 d-cache-block-size = <64>;
73 d-cache-sets = <64>;
74 d-cache-size = <32768>;
75 d-tlb-sets = <1>;
76 d-tlb-size = <32>;
78 i-cache-block-size = <64>;
79 i-cache-sets = <64>;
80 i-cache-size = <32768>;
81 i-tlb-sets = <1>;
82 i-tlb-size = <32>;
83 mmu-type = "riscv,sv39";
86 riscv,isa-base = "rv64i";
87 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
90 tlb-split;
91 next-level-cache = <&cctrllr>;
94 cpu2_intc: interrupt-controller {
95 #interrupt-cells = <1>;
96 compatible = "riscv,cpu-intc";
97 interrupt-controller;
102 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
103 d-cache-block-size = <64>;
104 d-cache-sets = <64>;
105 d-cache-size = <32768>;
106 d-tlb-sets = <1>;
107 d-tlb-size = <32>;
109 i-cache-block-size = <64>;
110 i-cache-sets = <64>;
111 i-cache-size = <32768>;
112 i-tlb-sets = <1>;
113 i-tlb-size = <32>;
114 mmu-type = "riscv,sv39";
117 riscv,isa-base = "rv64i";
118 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
121 tlb-split;
122 next-level-cache = <&cctrllr>;
125 cpu3_intc: interrupt-controller {
126 #interrupt-cells = <1>;
127 compatible = "riscv,cpu-intc";
128 interrupt-controller;
133 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
134 d-cache-block-size = <64>;
135 d-cache-sets = <64>;
136 d-cache-size = <32768>;
137 d-tlb-sets = <1>;
138 d-tlb-size = <32>;
140 i-cache-block-size = <64>;
141 i-cache-sets = <64>;
142 i-cache-size = <32768>;
143 i-tlb-sets = <1>;
144 i-tlb-size = <32>;
145 mmu-type = "riscv,sv39";
148 riscv,isa-base = "rv64i";
149 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
152 tlb-split;
153 next-level-cache = <&cctrllr>;
155 cpu4_intc: interrupt-controller {
156 #interrupt-cells = <1>;
157 compatible = "riscv,cpu-intc";
158 interrupt-controller;
162 cpu-map {
188 compatible = "fixed-clock";
189 #clock-cells = <0>;
193 compatible = "microchip,mpfs-sys-controller";
198 compatible = "fixed-clock";
199 #clock-cells = <0>;
200 clock-frequency = <80000000>;
204 #address-cells = <2>;
205 #size-cells = <2>;
206 compatible = "simple-bus";
209 cctrllr: cache-controller@2010000 {
210 compatible = "microchip,mpfs-ccache", "sifive,fu540-c000-ccache", "cache";
212 cache-block-size = <64>;
213 cache-level = <2>;
214 cache-sets = <1024>;
215 cache-size = <2097152>;
216 cache-unified;
217 interrupt-parent = <&plic>;
222 compatible = "sifive,fu540-c000-clint", "sifive,clint0";
224 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
231 plic: interrupt-controller@c000000 {
232 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
234 #address-cells = <0>;
235 #interrupt-cells = <1>;
236 interrupt-controller;
237 interrupts-extended = <&cpu0_intc 11>,
245 pdma: dma-controller@3000000 {
246 compatible = "microchip,mpfs-pdma", "sifive,pdma0";
248 interrupt-parent = <&plic>;
250 dma-channels = <4>;
251 #dma-cells = <1>;
255 compatible = "microchip,mpfs-clkcfg";
258 #clock-cells = <1>;
259 #reset-cells = <1>;
262 ccc_se: clock-controller@38010000 {
263 compatible = "microchip,mpfs-ccc";
266 #clock-cells = <1>;
270 ccc_ne: clock-controller@38040000 {
271 compatible = "microchip,mpfs-ccc";
274 #clock-cells = <1>;
278 ccc_nw: clock-controller@38100000 {
279 compatible = "microchip,mpfs-ccc";
282 #clock-cells = <1>;
286 ccc_sw: clock-controller@38400000 {
287 compatible = "microchip,mpfs-ccc";
290 #clock-cells = <1>;
297 reg-io-width = <4>;
298 reg-shift = <2>;
299 interrupt-parent = <&plic>;
301 current-speed = <115200>;
309 reg-io-width = <4>;
310 reg-shift = <2>;
311 interrupt-parent = <&plic>;
313 current-speed = <115200>;
321 reg-io-width = <4>;
322 reg-shift = <2>;
323 interrupt-parent = <&plic>;
325 current-speed = <115200>;
333 reg-io-width = <4>;
334 reg-shift = <2>;
335 interrupt-parent = <&plic>;
337 current-speed = <115200>;
345 reg-io-width = <4>;
346 reg-shift = <2>;
347 interrupt-parent = <&plic>;
350 current-speed = <115200>;
356 compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc";
358 interrupt-parent = <&plic>;
361 max-frequency = <200000000>;
366 compatible = "microchip,mpfs-spi";
367 #address-cells = <1>;
368 #size-cells = <0>;
370 interrupt-parent = <&plic>;
377 compatible = "microchip,mpfs-spi";
378 #address-cells = <1>;
379 #size-cells = <0>;
381 interrupt-parent = <&plic>;
388 compatible = "microchip,mpfs-qspi", "microchip,coreqspi-rtl-v2";
389 #address-cells = <1>;
390 #size-cells = <0>;
392 interrupt-parent = <&plic>;
399 compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
401 #address-cells = <1>;
402 #size-cells = <0>;
403 interrupt-parent = <&plic>;
406 clock-frequency = <100000>;
411 compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
413 #address-cells = <1>;
414 #size-cells = <0>;
415 interrupt-parent = <&plic>;
418 clock-frequency = <100000>;
423 compatible = "microchip,mpfs-can";
426 interrupt-parent = <&plic>;
432 compatible = "microchip,mpfs-can";
435 interrupt-parent = <&plic>;
441 compatible = "microchip,mpfs-macb", "cdns,macb";
443 #address-cells = <1>;
444 #size-cells = <0>;
445 interrupt-parent = <&plic>;
447 local-mac-address = [00 00 00 00 00 00];
449 clock-names = "pclk", "hclk";
455 compatible = "microchip,mpfs-macb", "cdns,macb";
457 #address-cells = <1>;
458 #size-cells = <0>;
459 interrupt-parent = <&plic>;
461 local-mac-address = [00 00 00 00 00 00];
463 clock-names = "pclk", "hclk";
469 compatible = "microchip,mpfs-gpio";
471 interrupt-parent = <&plic>;
472 interrupt-controller;
473 #interrupt-cells = <1>;
475 gpio-controller;
476 #gpio-cells = <2>;
481 compatible = "microchip,mpfs-gpio";
483 interrupt-parent = <&plic>;
484 interrupt-controller;
485 #interrupt-cells = <1>;
487 gpio-controller;
488 #gpio-cells = <2>;
493 compatible = "microchip,mpfs-gpio";
495 interrupt-parent = <&plic>;
496 interrupt-controller;
497 #interrupt-cells = <1>;
499 gpio-controller;
500 #gpio-cells = <2>;
505 compatible = "microchip,mpfs-rtc";
507 interrupt-parent = <&plic>;
510 clock-names = "rtc", "rtcref";
515 compatible = "microchip,mpfs-musb";
517 interrupt-parent = <&plic>;
520 interrupt-names = "dma","mc";
525 compatible = "microchip,mpfs-mailbox";
528 interrupt-parent = <&plic>;
530 #mbox-cells = <1>;
535 compatible = "microchip,mpfs-qspi", "microchip,coreqspi-rtl-v2";
536 #address-cells = <1>;
537 #size-cells = <0>;
539 interrupt-parent = <&plic>;