Lines Matching +full:mpfs +full:- +full:rtc
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
6 #include "mpfs.dtsi"
7 #include "mpfs-sev-kit-fabric.dtsi"
10 #address-cells = <2>;
11 #size-cells = <2>;
12 model = "Microchip PolarFire-SoC SEV Kit";
13 compatible = "microchip,mpfs-sev-kit", "microchip,mpfs";
25 stdout-path = "serial1:115200n8";
28 reserved-memory {
29 #address-cells = <2>;
30 #size-cells = <2>;
34 compatible = "shared-dma-pool";
39 compatible = "shared-dma-pool";
44 compatible = "shared-dma-pool";
73 phy-mode = "sgmii";
74 phy-handle = <&phy0>;
75 phy1: ethernet-phy@9 {
78 phy0: ethernet-phy@8 {
85 phy-mode = "sgmii";
86 phy-handle = <&phy1>;
95 bus-width = <4>;
96 disable-wp;
97 cap-sd-highspeed;
98 cap-mmc-highspeed;
99 mmc-ddr-1_8v;
100 mmc-hs200-1_8v;
101 sd-uhs-sdr12;
102 sd-uhs-sdr25;
103 sd-uhs-sdr50;
104 sd-uhs-sdr104;
124 clock-frequency = <125000000>;
127 &rtc {