Lines Matching full:is
5 This file is part of GDB, GAS, and the GNU binutils.
30 /* The opcode table is an array of struct powerpc_opcode. */
41 /* The opcode mask. This is used by the disassembler. This is a
57 /* An array of operand codes. Each code is an index into the
63 /* The table itself is sorted by major opcode number, and is otherwise
73 /* Opcode is defined for the PowerPC architecture. */
76 /* Opcode is defined for the POWER (RS/6000) architecture. */
79 /* Opcode is defined for the POWER2 (Rios 2) architecture. */
82 /* Opcode is supported by the Motorola PowerPC 601 processor. The 601
83 is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
87 /* Opcode is supported in both the Power and PowerPC architectures
94 /* Opcode is supported for any Power or PowerPC platform (this is
98 /* Opcode is only defined on 64 bit architectures. */
101 /* Opcode is supported as part of the 64-bit bridge. */
104 /* Opcode is supported by Altivec Vector Unit */
107 /* Opcode is supported by PowerPC 403 processor. */
110 /* Opcode is supported by PowerPC BookE processor. */
113 /* Opcode is supported by PowerPC 440 processor. */
116 /* Opcode is only supported by Power4 architecture. */
119 /* Opcode is only supported by Power7 architecture. */
122 /* Opcode is only supported by e500x2 Core. */
125 /* Opcode is supported by e500x2 Integer select APU. */
128 /* Opcode is an e500 SPE floating point instruction. */
131 /* Opcode is supported by branch locking APU. */
134 /* Opcode is supported by performance monitor APU. */
137 /* Opcode is supported by cache locking APU. */
140 /* Opcode is supported by machine check APU. */
143 /* Opcode is only supported by Power5 architecture. */
146 /* Opcode is supported by PowerPC e300 family. */
149 /* Opcode is only supported by Power6 architecture. */
152 /* Opcode is only supported by PowerPC Cell family. */
155 /* Opcode is supported by CPUs with paired singles support. */
158 /* Opcode is supported by Power E500MC */
161 /* Opcode is supported by PowerPC 405 processor. */
164 /* Opcode is supported by Vector-Scalar (VSX) Unit */
167 /* Opcode is supported by A2. */
170 /* Opcode is supported by PowerPC 476 processor. */
173 /* Opcode is supported by AppliedMicro Titan core */
176 /* Opcode which is supported by the e500 family */
179 /* Opcode is supported by Extended Altivec Vector Unit */
182 /* Opcode is supported by Power E6500 */
185 /* Opcode is supported by Thread management APU */
188 /* Opcode which is supported by the VLE extension. */
191 /* Opcode is only supported by Power8 architecture. */
194 /* Opcode which is supported by the Hardware Transactional Memory extension. */
195 /* Currently, this is the same as the POWER8 mask. If another cpu comes out
199 /* Opcode is supported by ppc750cl. */
202 /* Opcode is supported by ppc7450. */
205 /* Opcode is supported by ppc821/850/860. */
208 /* Opcode is only supported by Power9 architecture. */
211 /* Opcode is supported by Vector-Scalar (VSX) Unit from ISA 2.08. */
214 /* Opcode is supported by e200z4. */
220 /* A macro to determine if the instruction is a 2-byte VLE insn. */
229 /* The operands table is an array of struct powerpc_operand. */
237 is made if this is zero. For positive values, the operand
238 is shifted left by SHIFT. For negative values, the operand
239 is shifted right by -SHIFT. Use PPC_OPSHIFT_INV to indicate
244 /* Insertion function. This is used by the assembler. To insert an
247 If it is NULL, execute
252 (i is the instruction which we are filling in, o is a pointer to
253 this structure, and op is the operand value).
255 If this field is not NULL, then simply call it with the
257 of the instruction. If the ERRMSG argument is not NULL, then if
258 the operand value is illegal, *ERRMSG will be set to a warning
260 operand value is legal, *ERRMSG will be unchanged (most operands
265 /* Extraction function. This is used by the disassembler. To
268 If it is NULL, compute
275 (i is the instruction, o is a pointer to this structure, and op
276 is the result).
278 If this field is not NULL, then simply call it with the
280 the INVALID argument is not NULL, *INVALID will be set to
283 operand is valid, *INVALID will not be changed. */
307 range of values when running in 32 bit mode. That is, if bits is
309 this flag is ignored. */
313 is used to support extended mnemonics such as mr, for which two
321 separated from this one by a comma. This is used for the load and
347 /* This operand is a relative branch displacement. The disassembler
351 /* This operand is an absolute branch address. The disassembler
355 /* This operand is optional, and is zero if omitted. This is used for
359 whether this operand is present or not. The disassembler should
360 print this operand out only if it is not zero. */
363 /* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
364 is omitted, then for the next operand use this operand value plus
366 hack is needed because the Power rotate instructions can take
373 number is disallowed and one more than the normal most positive
374 number is allowed). This flag will only be set for a signed
382 /* This operand is for the DS field in a DS form instruction. */
385 /* This operand is for the DQ field in a DQ form instruction. */
388 /* Valid range of operand is 0..n rather than 0..n-1. */
400 /* This is a CR FIELD that does not use symbolic names. */
403 /* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
404 is omitted, then the value it should use for the operand is stored
408 /* This flag is only used with PPC_OPERAND_OPTIONAL. The operand is
413 with the operands table for simplicity. The macro table is an
430 Each %N in the string is replaced with operand number N (zero