1 // SPDX-License-Identifier: GPL-2.0-or-later
3  * MPIC timer driver
41 #define MAX_TICKS			(~0U >> 1)
43 #define TIMER_OFFSET(num)		(1 << (TIMERS_PER_GROUP - 1 - num))
59 	unsigned int timer_num;		/* cascade control timer */
64 	struct mpic_timer		timer[TIMERS_PER_GROUP];  member
74 	/* cascade timer 0 and 1 */
76 	/* cascade timer 1 and 2 */
78 	/* cascade timer 2 and 3 */
87 	*time = (u64)div_u64(ticks, priv->timerfreq);  in convert_ticks_to_time()
96 	max_value = div_u64(ULLONG_MAX, priv->timerfreq);  in convert_time_to_ticks()
99 		return -EINVAL;  in convert_time_to_ticks()
101 	*ticks = (u64)time * (u64)priv->timerfreq;  in convert_time_to_ticks()
106 /* detect whether there is a cascade timer available */
119 		spin_lock_irqsave(&priv->lock, flags);  in detect_idle_cascade_timer()
120 		map = casc_priv->cascade_map & priv->idle;  in detect_idle_cascade_timer()
121 		if (map == casc_priv->cascade_map) {  in detect_idle_cascade_timer()
122 			num = casc_priv->timer_num;  in detect_idle_cascade_timer()
123 			priv->timer[num].cascade_handle = casc_priv;  in detect_idle_cascade_timer()
125 			/* set timer busy */  in detect_idle_cascade_timer()
126 			priv->idle &= ~casc_priv->cascade_map;  in detect_idle_cascade_timer()
127 			spin_unlock_irqrestore(&priv->lock, flags);  in detect_idle_cascade_timer()
128 			return &priv->timer[num];  in detect_idle_cascade_timer()
130 		spin_unlock_irqrestore(&priv->lock, flags);  in detect_idle_cascade_timer()
146 	casc_priv = priv->timer[num].cascade_handle;  in set_cascade_timer()
148 		return -EINVAL;  in set_cascade_timer()
150 	tcr = casc_priv->tcr_value |  in set_cascade_timer()
151 		(casc_priv->tcr_value << MPIC_TIMER_TCR_ROVR_OFFSET);  in set_cascade_timer()
152 	setbits32(priv->group_tcr, tcr);  in set_cascade_timer()
156 	out_be32(&priv->regs[num].gtccr, 0);  in set_cascade_timer()
157 	out_be32(&priv->regs[num].gtbcr, tmp_ticks | TIMER_STOP);  in set_cascade_timer()
159 	out_be32(&priv->regs[num - 1].gtccr, 0);  in set_cascade_timer()
160 	out_be32(&priv->regs[num - 1].gtbcr, rem_ticks);  in set_cascade_timer()
177 	/* detect idle timer */  in get_cascade_timer()
182 	/* set ticks to timer */  in get_cascade_timer()
183 	ret = set_cascade_timer(priv, ticks, allocated_timer->num);  in get_cascade_timer()
193 	struct mpic_timer *timer;  in get_timer()  local
207 			if (!(priv->flags & FSL_GLOBAL_TIMER))  in get_timer()
210 			timer = get_cascade_timer(priv, ticks);  in get_timer()
211 			if (!timer)  in get_timer()
214 			return timer;  in get_timer()
218 			/* one timer: Reverse allocation */  in get_timer()
219 			num = TIMERS_PER_GROUP - 1 - i;  in get_timer()
220 			spin_lock_irqsave(&priv->lock, flags);  in get_timer()
221 			if (priv->idle & (1 << i)) {  in get_timer()
222 				/* set timer busy */  in get_timer()
223 				priv->idle &= ~(1 << i);  in get_timer()
224 				/* set ticks & stop timer */  in get_timer()
225 				out_be32(&priv->regs[num].gtbcr,  in get_timer()
227 				out_be32(&priv->regs[num].gtccr, 0);  in get_timer()
228 				priv->timer[num].cascade_handle = NULL;  in get_timer()
229 				spin_unlock_irqrestore(&priv->lock, flags);  in get_timer()
230 				return &priv->timer[num];  in get_timer()
232 			spin_unlock_irqrestore(&priv->lock, flags);  in get_timer()
240  * mpic_start_timer - start hardware timer
241  * @handle: the timer to be started.
243  * It will do ->fn(->dev) callback from the hardware interrupt at
249 			struct timer_group_priv, timer[handle->num]);  in mpic_start_timer()
251 	clrbits32(&priv->regs[handle->num].gtbcr, TIMER_STOP);  in mpic_start_timer()
256  * mpic_stop_timer - stop hardware timer
257  * @handle: the timer to be stopped
259  * The timer periodically generates an interrupt. Unless user stops the timer.
264 			struct timer_group_priv, timer[handle->num]);  in mpic_stop_timer()
267 	setbits32(&priv->regs[handle->num].gtbcr, TIMER_STOP);  in mpic_stop_timer()
269 	casc_priv = priv->timer[handle->num].cascade_handle;  in mpic_stop_timer()
271 		out_be32(&priv->regs[handle->num].gtccr, 0);  in mpic_stop_timer()
272 		out_be32(&priv->regs[handle->num - 1].gtccr, 0);  in mpic_stop_timer()
274 		out_be32(&priv->regs[handle->num].gtccr, 0);  in mpic_stop_timer()
280  * mpic_get_remain_time - get timer time
281  * @handle: the timer to be selected.
282  * @time: time for timer
284  * Query timer remaining time.
289 			struct timer_group_priv, timer[handle->num]);  in mpic_get_remain_time()
295 	casc_priv = priv->timer[handle->num].cascade_handle;  in mpic_get_remain_time()
297 		tmp_ticks = in_be32(&priv->regs[handle->num].gtccr);  in mpic_get_remain_time()
300 		tmp_ticks = in_be32(&priv->regs[handle->num - 1].gtccr);  in mpic_get_remain_time()
303 		ticks = in_be32(&priv->regs[handle->num].gtccr);  in mpic_get_remain_time()
312  * mpic_free_timer - free hardware timer
313  * @handle: the timer to be removed.
315  * Free the timer.
322 			struct timer_group_priv, timer[handle->num]);  in mpic_free_timer()
329 	casc_priv = priv->timer[handle->num].cascade_handle;  in mpic_free_timer()
331 	free_irq(priv->timer[handle->num].irq, priv->timer[handle->num].dev);  in mpic_free_timer()
333 	spin_lock_irqsave(&priv->lock, flags);  in mpic_free_timer()
336 		tcr = casc_priv->tcr_value | (casc_priv->tcr_value <<  in mpic_free_timer()
338 		clrbits32(priv->group_tcr, tcr);  in mpic_free_timer()
339 		priv->idle |= casc_priv->cascade_map;  in mpic_free_timer()
340 		priv->timer[handle->num].cascade_handle = NULL;  in mpic_free_timer()
342 		priv->idle |= TIMER_OFFSET(handle->num);  in mpic_free_timer()
344 	spin_unlock_irqrestore(&priv->lock, flags);  in mpic_free_timer()
349  * mpic_request_timer - get a hardware timer
352  * @time: time for timer
373 	ret = request_irq(allocated_timer->irq, fn,  in mpic_request_timer()
374 			IRQF_TRIGGER_LOW, "global-timer", dev);  in mpic_request_timer()
380 	allocated_timer->dev = dev;  in mpic_request_timer()
391 	if (priv->flags & FSL_GLOBAL_TIMER) {  in timer_group_get_freq()
396 			of_property_read_u32(dn, "clock-frequency",  in timer_group_get_freq()
397 					&priv->timerfreq);  in timer_group_get_freq()
402 	if (priv->timerfreq <= 0)  in timer_group_get_freq()
403 		return -EINVAL;  in timer_group_get_freq()
405 	if (priv->flags & FSL_GLOBAL_TIMER) {  in timer_group_get_freq()
406 		div = (1 << (MPIC_TIMER_TCR_CLKDIV >> 8)) * 8;  in timer_group_get_freq()
407 		priv->timerfreq /= div;  in timer_group_get_freq()
427 	p = of_get_property(np, "fsl,available-ranges", &len);  in timer_group_get_irq()
429 		pr_err("%pOF: malformed available-ranges property.\n", np);  in timer_group_get_irq()
430 		return -EINVAL;  in timer_group_get_irq()
442 		count = p[i * 2 + 1];  in timer_group_get_irq()
447 				return -EINVAL;  in timer_group_get_irq()
450 			/* Set timer idle */  in timer_group_get_irq()
451 			priv->idle |= TIMER_OFFSET((offset + j));  in timer_group_get_irq()
452 			priv->timer[offset + j].irq = irq;  in timer_group_get_irq()
453 			priv->timer[offset + j].num = offset + j;  in timer_group_get_irq()
473 	if (of_device_is_compatible(np, "fsl,mpic-global-timer"))  in timer_group_init()
474 		priv->flags |= FSL_GLOBAL_TIMER;  in timer_group_init()
476 	priv->regs = of_iomap(np, i++);  in timer_group_init()
477 	if (!priv->regs) {  in timer_group_init()
478 		pr_err("%pOF: cannot ioremap timer register address.\n", np);  in timer_group_init()
482 	if (priv->flags & FSL_GLOBAL_TIMER) {  in timer_group_init()
483 		priv->group_tcr = of_iomap(np, i++);  in timer_group_init()
484 		if (!priv->group_tcr) {  in timer_group_init()
492 		pr_err("%pOF: cannot get timer frequency.\n", np);  in timer_group_init()
498 		pr_err("%pOF: cannot get timer irqs.\n", np);  in timer_group_init()
502 	spin_lock_init(&priv->lock);  in timer_group_init()
504 	/* Init FSL timer hardware */  in timer_group_init()
505 	if (priv->flags & FSL_GLOBAL_TIMER)  in timer_group_init()
506 		setbits32(priv->group_tcr, MPIC_TIMER_TCR_CLKDIV);  in timer_group_init()
508 	list_add_tail(&priv->node, &timer_group_list);  in timer_group_init()
513 	if (priv->regs)  in timer_group_init()
514 		iounmap(priv->regs);  in timer_group_init()
516 	if (priv->group_tcr)  in timer_group_init()
517 		iounmap(priv->group_tcr);  in timer_group_init()
527 		/* Init FSL timer hardware */  in mpic_timer_resume()
528 		if (priv->flags & FSL_GLOBAL_TIMER)  in mpic_timer_resume()
529 			setbits32(priv->group_tcr, MPIC_TIMER_TCR_CLKDIV);  in mpic_timer_resume()
534 	{ .compatible = "fsl,mpic-global-timer", },
552 		return -ENODEV;  in mpic_timer_init()