Lines Matching +full:mpic +full:- +full:msi +full:- +full:v4
2 * arch/powerpc/kernel/mpic.c
5 * common implementation being IBM's MPIC. This driver also can deal
9 * Copyright 2010-2012 Freescale Semiconductor, Inc.
42 #include <asm/mpic.h>
45 #include "mpic.h"
54 .name = "mpic",
55 .dev_name = "mpic",
59 static struct mpic *mpics;
60 static struct mpic *mpic_primary;
73 [0] = { /* Original OpenPIC compatible MPIC */
153 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
161 static inline unsigned int mpic_processor_id(struct mpic *mpic) in mpic_processor_id() argument
165 if (!(mpic->flags & MPIC_SECONDARY)) in mpic_processor_id()
183 return dcr_read(rb->dhost, reg); in _mpic_read()
186 return in_be32(rb->base + (reg >> 2)); in _mpic_read()
189 return in_le32(rb->base + (reg >> 2)); in _mpic_read()
200 dcr_write(rb->dhost, reg, value); in _mpic_write()
204 out_be32(rb->base + (reg >> 2), value); in _mpic_write()
208 out_le32(rb->base + (reg >> 2), value); in _mpic_write()
213 static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi) in _mpic_ipi_read() argument
215 enum mpic_reg_type type = mpic->reg_type; in _mpic_ipi_read()
219 if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le) in _mpic_ipi_read()
221 return _mpic_read(type, &mpic->gregs, offset); in _mpic_ipi_read()
224 static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value) in _mpic_ipi_write() argument
229 _mpic_write(mpic->reg_type, &mpic->gregs, offset, value); in _mpic_ipi_write()
232 static inline unsigned int mpic_tm_offset(struct mpic *mpic, unsigned int tm) in mpic_tm_offset() argument
238 static inline u32 _mpic_tm_read(struct mpic *mpic, unsigned int tm) in _mpic_tm_read() argument
240 unsigned int offset = mpic_tm_offset(mpic, tm) + in _mpic_tm_read()
243 return _mpic_read(mpic->reg_type, &mpic->tmregs, offset); in _mpic_tm_read()
246 static inline void _mpic_tm_write(struct mpic *mpic, unsigned int tm, u32 value) in _mpic_tm_write() argument
248 unsigned int offset = mpic_tm_offset(mpic, tm) + in _mpic_tm_write()
251 _mpic_write(mpic->reg_type, &mpic->tmregs, offset, value); in _mpic_tm_write()
254 static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg) in _mpic_cpu_read() argument
256 unsigned int cpu = mpic_processor_id(mpic); in _mpic_cpu_read()
258 return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg); in _mpic_cpu_read()
261 static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value) in _mpic_cpu_write() argument
263 unsigned int cpu = mpic_processor_id(mpic); in _mpic_cpu_write()
265 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value); in _mpic_cpu_write()
268 static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg) in _mpic_irq_read() argument
270 unsigned int isu = src_no >> mpic->isu_shift; in _mpic_irq_read()
271 unsigned int idx = src_no & mpic->isu_mask; in _mpic_irq_read()
274 val = _mpic_read(mpic->reg_type, &mpic->isus[isu], in _mpic_irq_read()
279 mpic->isu_reg0_shadow[src_no]; in _mpic_irq_read()
284 static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no, in _mpic_irq_write() argument
287 unsigned int isu = src_no >> mpic->isu_shift; in _mpic_irq_write()
288 unsigned int idx = src_no & mpic->isu_mask; in _mpic_irq_write()
290 _mpic_write(mpic->reg_type, &mpic->isus[isu], in _mpic_irq_write()
295 mpic->isu_reg0_shadow[src_no] = in _mpic_irq_write()
300 #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r))
301 #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v))
302 #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))
303 #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))
304 #define mpic_tm_read(i) _mpic_tm_read(mpic,(i))
305 #define mpic_tm_write(i,v) _mpic_tm_write(mpic,(i),(v))
306 #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))
307 #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))
308 #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))
309 #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v))
317 static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr, in _mpic_map_mmio() argument
321 rb->base = ioremap(phys_addr + offset, size); in _mpic_map_mmio()
322 BUG_ON(rb->base == NULL); in _mpic_map_mmio()
326 static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb, in _mpic_map_dcr() argument
329 phys_addr_t phys_addr = dcr_resource_start(mpic->node, 0); in _mpic_map_dcr()
330 rb->dhost = dcr_map(mpic->node, phys_addr + offset, size); in _mpic_map_dcr()
331 BUG_ON(!DCR_MAP_OK(rb->dhost)); in _mpic_map_dcr()
334 static inline void mpic_map(struct mpic *mpic, in mpic_map() argument
338 if (mpic->flags & MPIC_USES_DCR) in mpic_map()
339 _mpic_map_dcr(mpic, rb, offset, size); in mpic_map()
341 _mpic_map_mmio(mpic, phys_addr, rb, offset, size); in mpic_map()
352 static void __init mpic_test_broken_ipi(struct mpic *mpic) in mpic_test_broken_ipi() argument
356 mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK); in mpic_test_broken_ipi()
357 r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0)); in mpic_test_broken_ipi()
360 printk(KERN_INFO "mpic: Detected reversed IPI registers\n"); in mpic_test_broken_ipi()
361 mpic->flags |= MPIC_BROKEN_IPI; in mpic_test_broken_ipi()
368 * to force the edge setting on the MPIC and do the ack workaround.
370 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) in mpic_is_ht_interrupt() argument
372 if (source >= 128 || !mpic->fixups) in mpic_is_ht_interrupt()
374 return mpic->fixups[source].base != NULL; in mpic_is_ht_interrupt()
378 static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source) in mpic_ht_end_irq() argument
380 struct mpic_irq_fixup *fixup = &mpic->fixups[source]; in mpic_ht_end_irq()
382 if (fixup->applebase) { in mpic_ht_end_irq()
383 unsigned int soff = (fixup->index >> 3) & ~3; in mpic_ht_end_irq()
384 unsigned int mask = 1U << (fixup->index & 0x1f); in mpic_ht_end_irq()
385 writel(mask, fixup->applebase + soff); in mpic_ht_end_irq()
387 raw_spin_lock(&mpic->fixup_lock); in mpic_ht_end_irq()
388 writeb(0x11 + 2 * fixup->index, fixup->base + 2); in mpic_ht_end_irq()
389 writel(fixup->data, fixup->base + 4); in mpic_ht_end_irq()
390 raw_spin_unlock(&mpic->fixup_lock); in mpic_ht_end_irq()
394 static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source, in mpic_startup_ht_interrupt() argument
397 struct mpic_irq_fixup *fixup = &mpic->fixups[source]; in mpic_startup_ht_interrupt()
401 if (fixup->base == NULL) in mpic_startup_ht_interrupt()
405 source, fixup->index); in mpic_startup_ht_interrupt()
406 raw_spin_lock_irqsave(&mpic->fixup_lock, flags); in mpic_startup_ht_interrupt()
408 writeb(0x10 + 2 * fixup->index, fixup->base + 2); in mpic_startup_ht_interrupt()
409 tmp = readl(fixup->base + 4); in mpic_startup_ht_interrupt()
413 writel(tmp, fixup->base + 4); in mpic_startup_ht_interrupt()
414 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags); in mpic_startup_ht_interrupt()
419 mpic->save_data[source].fixup_data = tmp | 1; in mpic_startup_ht_interrupt()
423 static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source) in mpic_shutdown_ht_interrupt() argument
425 struct mpic_irq_fixup *fixup = &mpic->fixups[source]; in mpic_shutdown_ht_interrupt()
429 if (fixup->base == NULL) in mpic_shutdown_ht_interrupt()
435 raw_spin_lock_irqsave(&mpic->fixup_lock, flags); in mpic_shutdown_ht_interrupt()
436 writeb(0x10 + 2 * fixup->index, fixup->base + 2); in mpic_shutdown_ht_interrupt()
437 tmp = readl(fixup->base + 4); in mpic_shutdown_ht_interrupt()
439 writel(tmp, fixup->base + 4); in mpic_shutdown_ht_interrupt()
440 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags); in mpic_shutdown_ht_interrupt()
445 mpic->save_data[source].fixup_data = tmp & ~1; in mpic_shutdown_ht_interrupt()
450 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase, in mpic_scan_ht_msi() argument
478 pr_debug("mpic: - HT:%02x.%x %s MSI mapping found @ 0x%llx\n", in mpic_scan_ht_msi()
486 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase, in mpic_scan_ht_msi() argument
493 static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase, in mpic_scan_ht_pic() argument
517 printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x" in mpic_scan_ht_pic()
529 mpic->fixups[irq].index = i; in mpic_scan_ht_pic()
530 mpic->fixups[irq].base = base; in mpic_scan_ht_pic()
531 /* Apple HT PIC has a non-standard way of doing EOIs */ in mpic_scan_ht_pic()
533 mpic->fixups[irq].applebase = devbase + 0x60; in mpic_scan_ht_pic()
535 mpic->fixups[irq].applebase = NULL; in mpic_scan_ht_pic()
537 mpic->fixups[irq].data = readl(base + 4) | 0x80000000; in mpic_scan_ht_pic()
542 static void __init mpic_scan_ht_pics(struct mpic *mpic) in mpic_scan_ht_pics() argument
547 printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n"); in mpic_scan_ht_pics()
550 mpic->fixups = kcalloc(128, sizeof(*mpic->fixups), GFP_KERNEL); in mpic_scan_ht_pics()
551 BUG_ON(mpic->fixups == NULL); in mpic_scan_ht_pics()
554 raw_spin_lock_init(&mpic->fixup_lock); in mpic_scan_ht_pics()
556 /* Map U3 config space. We assume all IO-APICs are on the primary bus in mpic_scan_ht_pics()
582 mpic_scan_ht_pic(mpic, devbase, devfn, l); in mpic_scan_ht_pics()
583 mpic_scan_ht_msi(mpic, devbase, devfn); in mpic_scan_ht_pics()
594 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source) in mpic_is_ht_interrupt() argument
599 static void __init mpic_scan_ht_pics(struct mpic *mpic) in mpic_scan_ht_pics() argument
605 /* Find an mpic associated with a given linux interrupt */
606 static struct mpic *mpic_find(unsigned int irq) in mpic_find()
615 static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int src) in mpic_is_ipi() argument
617 return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]); in mpic_is_ipi()
621 static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int src) in mpic_is_tm() argument
623 return (src >= mpic->timer_vecs[0] && src <= mpic->timer_vecs[7]); in mpic_is_tm()
638 /* Get the mpic structure from the IPI number */
639 static inline struct mpic * mpic_from_ipi(struct irq_data *d) in mpic_from_ipi()
645 /* Get the mpic structure from the irq number */
646 static inline struct mpic * mpic_from_irq(unsigned int irq) in mpic_from_irq()
651 /* Get the mpic structure from the irq data */
652 static inline struct mpic * mpic_from_irq_data(struct irq_data *d) in mpic_from_irq_data()
658 static inline void mpic_eoi(struct mpic *mpic) in mpic_eoi() argument
671 struct mpic *mpic = mpic_from_irq_data(d); in mpic_unmask_irq() local
674 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src); in mpic_unmask_irq()
681 if (!loops--) { in mpic_unmask_irq()
692 struct mpic *mpic = mpic_from_irq_data(d); in mpic_mask_irq() local
695 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src); in mpic_mask_irq()
703 if (!loops--) { in mpic_mask_irq()
713 struct mpic *mpic = mpic_from_irq_data(d); in mpic_end_irq() local
716 DBG("%s: end_irq: %d\n", mpic->name, d->irq); in mpic_end_irq()
719 * should only lower the priority, the MPIC should have properly in mpic_end_irq()
723 mpic_eoi(mpic); in mpic_end_irq()
730 struct mpic *mpic = mpic_from_irq_data(d); in mpic_unmask_ht_irq() local
736 mpic_ht_end_irq(mpic, src); in mpic_unmask_ht_irq()
741 struct mpic *mpic = mpic_from_irq_data(d); in mpic_startup_ht_irq() local
745 mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d)); in mpic_startup_ht_irq()
752 struct mpic *mpic = mpic_from_irq_data(d); in mpic_shutdown_ht_irq() local
755 mpic_shutdown_ht_interrupt(mpic, src); in mpic_shutdown_ht_irq()
761 struct mpic *mpic = mpic_from_irq_data(d); in mpic_end_ht_irq() local
765 DBG("%s: end_irq: %d\n", mpic->name, d->irq); in mpic_end_ht_irq()
768 * should only lower the priority, the MPIC should have properly in mpic_end_ht_irq()
773 mpic_ht_end_irq(mpic, src); in mpic_end_ht_irq()
774 mpic_eoi(mpic); in mpic_end_ht_irq()
782 struct mpic *mpic = mpic_from_ipi(d); in mpic_unmask_ipi() local
783 unsigned int src = virq_to_hw(d->irq) - mpic->ipi_vecs[0]; in mpic_unmask_ipi()
785 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src); in mpic_unmask_ipi()
796 struct mpic *mpic = mpic_from_ipi(d); in mpic_end_ipi() local
801 * applying to them. We EOI them late to avoid re-entering. in mpic_end_ipi()
803 mpic_eoi(mpic); in mpic_end_ipi()
810 struct mpic *mpic = mpic_from_irq_data(d); in mpic_unmask_tm() local
811 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0]; in mpic_unmask_tm()
813 DBG("%s: enable_tm: %d (tm %d)\n", mpic->name, d->irq, src); in mpic_unmask_tm()
820 struct mpic *mpic = mpic_from_irq_data(d); in mpic_mask_tm() local
821 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0]; in mpic_mask_tm()
830 struct mpic *mpic = mpic_from_irq_data(d); in mpic_set_affinity() local
833 if (mpic->flags & MPIC_SINGLE_DEST_CPU) { in mpic_set_affinity()
849 static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type) in mpic_type_to_vecpri() argument
872 struct mpic *mpic = mpic_from_irq_data(d); in mpic_set_irq_type() local
876 DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n", in mpic_set_irq_type()
877 mpic, d->irq, src, flow_type); in mpic_set_irq_type()
879 if (src >= mpic->num_sources) in mpic_set_irq_type()
880 return -EINVAL; in mpic_set_irq_type()
908 WARN_ONCE(1, "mpic: unknown IRQ type %d\n", vold); in mpic_set_irq_type()
915 if (mpic_is_ht_interrupt(mpic, src)) in mpic_set_irq_type()
919 vecpri = mpic_type_to_vecpri(mpic, flow_type); in mpic_set_irq_type()
932 struct mpic *mpic = mpic_from_irq(virq); in mpic_set_vector() local
936 DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n", in mpic_set_vector()
937 mpic, virq, src, vector); in mpic_set_vector()
939 if (src >= mpic->num_sources) in mpic_set_vector()
950 struct mpic *mpic = mpic_from_irq(virq); in mpic_set_destination() local
953 DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n", in mpic_set_destination()
954 mpic, virq, src, cpuid); in mpic_set_destination()
956 if (src >= mpic->num_sources) in mpic_set_destination()
998 /* Exact match, unless mpic node is NULL */ in mpic_host_match()
1006 struct mpic *mpic = h->host_data; in mpic_host_map() local
1009 DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw); in mpic_host_map()
1011 if (hw == mpic->spurious_vec) in mpic_host_map()
1012 return -EINVAL; in mpic_host_map()
1013 if (mpic->protected && test_bit(hw, mpic->protected)) { in mpic_host_map()
1014 pr_warn("mpic: Mapping of source 0x%x failed, source protected by firmware !\n", in mpic_host_map()
1016 return -EPERM; in mpic_host_map()
1020 else if (hw >= mpic->ipi_vecs[0]) { in mpic_host_map()
1021 WARN_ON(mpic->flags & MPIC_SECONDARY); in mpic_host_map()
1023 DBG("mpic: mapping as IPI\n"); in mpic_host_map()
1024 irq_set_chip_data(virq, mpic); in mpic_host_map()
1025 irq_set_chip_and_handler(virq, &mpic->hc_ipi, in mpic_host_map()
1031 if (hw >= mpic->timer_vecs[0] && hw <= mpic->timer_vecs[7]) { in mpic_host_map()
1032 WARN_ON(mpic->flags & MPIC_SECONDARY); in mpic_host_map()
1034 DBG("mpic: mapping as timer\n"); in mpic_host_map()
1035 irq_set_chip_data(virq, mpic); in mpic_host_map()
1036 irq_set_chip_and_handler(virq, &mpic->hc_tm, in mpic_host_map()
1041 if (mpic_map_error_int(mpic, virq, hw)) in mpic_host_map()
1044 if (hw >= mpic->num_sources) { in mpic_host_map()
1045 pr_warn("mpic: Mapping of source 0x%x failed, source out of range !\n", in mpic_host_map()
1047 return -EINVAL; in mpic_host_map()
1050 mpic_msi_reserve_hwirq(mpic, hw); in mpic_host_map()
1053 chip = &mpic->hc_irq; in mpic_host_map()
1057 if (mpic_is_ht_interrupt(mpic, hw)) in mpic_host_map()
1058 chip = &mpic->hc_ht_irq; in mpic_host_map()
1061 DBG("mpic: mapping to irq chip @%p\n", chip); in mpic_host_map()
1063 irq_set_chip_data(virq, mpic); in mpic_host_map()
1069 /* If the MPIC was reset, then all vectors have already been in mpic_host_map()
1073 if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) { in mpic_host_map()
1077 cpu = mpic_processor_id(mpic); in mpic_host_map()
1093 struct mpic *mpic = h->host_data; in mpic_host_xlate() local
1102 if (intsize >= 4 && (mpic->flags & MPIC_FSL)) { in mpic_host_xlate()
1104 * Freescale MPIC with extended intspec: in mpic_host_xlate()
1106 * an "interrupt type". Fourth is type-specific data. in mpic_host_xlate()
1108 * See Documentation/devicetree/bindings/powerpc/fsl/mpic.txt in mpic_host_xlate()
1114 if (!(mpic->flags & MPIC_FSL_HAS_EIMR)) in mpic_host_xlate()
1117 if (intspec[3] >= ARRAY_SIZE(mpic->err_int_vecs)) in mpic_host_xlate()
1118 return -EINVAL; in mpic_host_xlate()
1120 *out_hwirq = mpic->err_int_vecs[intspec[3]]; in mpic_host_xlate()
1124 if (intspec[0] >= ARRAY_SIZE(mpic->ipi_vecs)) in mpic_host_xlate()
1125 return -EINVAL; in mpic_host_xlate()
1127 *out_hwirq = mpic->ipi_vecs[intspec[0]]; in mpic_host_xlate()
1130 if (intspec[0] >= ARRAY_SIZE(mpic->timer_vecs)) in mpic_host_xlate()
1131 return -EINVAL; in mpic_host_xlate()
1133 *out_hwirq = mpic->timer_vecs[intspec[0]]; in mpic_host_xlate()
1138 return -EINVAL; in mpic_host_xlate()
1161 DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n", in mpic_host_xlate()
1167 /* IRQ handler for a secondary MPIC cascaded from another IRQ controller */
1171 struct mpic *mpic = irq_desc_get_handler_data(desc); in mpic_cascade() local
1174 BUG_ON(!(mpic->flags & MPIC_SECONDARY)); in mpic_cascade()
1176 virq = mpic_get_one_irq(mpic); in mpic_cascade()
1180 chip->irq_eoi(&desc->irq_data); in mpic_cascade()
1189 static u32 fsl_mpic_get_version(struct mpic *mpic) in fsl_mpic_get_version() argument
1193 if (!(mpic->flags & MPIC_FSL)) in fsl_mpic_get_version()
1196 brr1 = _mpic_read(mpic->reg_type, &mpic->thiscpuregs, in fsl_mpic_get_version()
1208 struct mpic *mpic = mpic_primary; in fsl_mpic_primary_get_version() local
1210 if (mpic) in fsl_mpic_primary_get_version()
1211 return fsl_mpic_get_version(mpic); in fsl_mpic_primary_get_version()
1216 struct mpic * __init mpic_alloc(struct device_node *node, in mpic_alloc()
1224 struct mpic *mpic; in mpic_alloc() local
1231 /* Default MPIC search parameters */ in mpic_alloc()
1233 { .type = "open-pic", }, in mpic_alloc()
1234 { .compatible = "open-pic", }, in mpic_alloc()
1239 * If we were not passed a device-tree node, then perform the default in mpic_alloc()
1252 /* Check if it is DCR-based */ in mpic_alloc()
1253 if (of_property_read_bool(node, "dcr-reg")) { in mpic_alloc()
1263 /* Read extra device-tree properties into the flags variable */ in mpic_alloc()
1264 if (of_property_read_bool(node, "big-endian")) in mpic_alloc()
1266 if (of_property_read_bool(node, "pic-no-reset")) in mpic_alloc()
1268 if (of_property_read_bool(node, "single-cpu-affinity")) in mpic_alloc()
1270 if (of_device_is_compatible(node, "fsl,mpic")) { in mpic_alloc()
1276 mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL); in mpic_alloc()
1277 if (mpic == NULL) in mpic_alloc()
1280 mpic->name = name; in mpic_alloc()
1281 mpic->node = node; in mpic_alloc()
1282 mpic->paddr = phys_addr; in mpic_alloc()
1283 mpic->flags = flags; in mpic_alloc()
1285 mpic->hc_irq = mpic_irq_chip; in mpic_alloc()
1286 mpic->hc_irq.name = name; in mpic_alloc()
1287 if (!(mpic->flags & MPIC_SECONDARY)) in mpic_alloc()
1288 mpic->hc_irq.irq_set_affinity = mpic_set_affinity; in mpic_alloc()
1290 mpic->hc_ht_irq = mpic_irq_ht_chip; in mpic_alloc()
1291 mpic->hc_ht_irq.name = name; in mpic_alloc()
1292 if (!(mpic->flags & MPIC_SECONDARY)) in mpic_alloc()
1293 mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity; in mpic_alloc()
1297 mpic->hc_ipi = mpic_ipi_chip; in mpic_alloc()
1298 mpic->hc_ipi.name = name; in mpic_alloc()
1301 mpic->hc_tm = mpic_tm_chip; in mpic_alloc()
1302 mpic->hc_tm.name = name; in mpic_alloc()
1304 mpic->num_sources = 0; /* so far */ in mpic_alloc()
1306 if (mpic->flags & MPIC_LARGE_VECTORS) in mpic_alloc()
1311 mpic->timer_vecs[0] = intvec_top - 12; in mpic_alloc()
1312 mpic->timer_vecs[1] = intvec_top - 11; in mpic_alloc()
1313 mpic->timer_vecs[2] = intvec_top - 10; in mpic_alloc()
1314 mpic->timer_vecs[3] = intvec_top - 9; in mpic_alloc()
1315 mpic->timer_vecs[4] = intvec_top - 8; in mpic_alloc()
1316 mpic->timer_vecs[5] = intvec_top - 7; in mpic_alloc()
1317 mpic->timer_vecs[6] = intvec_top - 6; in mpic_alloc()
1318 mpic->timer_vecs[7] = intvec_top - 5; in mpic_alloc()
1319 mpic->ipi_vecs[0] = intvec_top - 4; in mpic_alloc()
1320 mpic->ipi_vecs[1] = intvec_top - 3; in mpic_alloc()
1321 mpic->ipi_vecs[2] = intvec_top - 2; in mpic_alloc()
1322 mpic->ipi_vecs[3] = intvec_top - 1; in mpic_alloc()
1323 mpic->spurious_vec = intvec_top; in mpic_alloc()
1326 psrc = of_get_property(mpic->node, "protected-sources", &psize); in mpic_alloc()
1329 mpic->protected = bitmap_zalloc(intvec_top + 1, GFP_KERNEL); in mpic_alloc()
1330 BUG_ON(mpic->protected == NULL); in mpic_alloc()
1334 __set_bit(psrc[i], mpic->protected); in mpic_alloc()
1339 mpic->hw_set = mpic_infos[MPIC_GET_REGSET(mpic->flags)]; in mpic_alloc()
1343 if (mpic->flags & MPIC_BIG_ENDIAN) in mpic_alloc()
1344 mpic->reg_type = mpic_access_mmio_be; in mpic_alloc()
1346 mpic->reg_type = mpic_access_mmio_le; in mpic_alloc()
1349 * An MPIC with a "dcr-reg" property must be accessed that way, but in mpic_alloc()
1353 if (mpic->flags & MPIC_USES_DCR) in mpic_alloc()
1354 mpic->reg_type = mpic_access_dcr; in mpic_alloc()
1356 BUG_ON(mpic->flags & MPIC_USES_DCR); in mpic_alloc()
1360 mpic_map(mpic, mpic->paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000); in mpic_alloc()
1361 mpic_map(mpic, mpic->paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000); in mpic_alloc()
1363 if (mpic->flags & MPIC_FSL) { in mpic_alloc()
1368 * magic per-cpu area -- and they don't even show up in the in mpic_alloc()
1369 * non-magic per-cpu copies that this driver normally uses. in mpic_alloc()
1371 mpic_map(mpic, mpic->paddr, &mpic->thiscpuregs, in mpic_alloc()
1374 fsl_version = fsl_mpic_get_version(mpic); in mpic_alloc()
1378 * was added in MPIC version 4.1. in mpic_alloc()
1385 * Available vector space = intvec_top - 13, where 13 in mpic_alloc()
1390 ret = mpic_setup_error_int(mpic, intvec_top - 13); in mpic_alloc()
1398 * EPR is only available starting with v4.0. To support in mpic_alloc()
1399 * platforms that don't know the MPIC version at compile-time, in mpic_alloc()
1400 * such as qemu-e500, turn off coreint if this MPIC doesn't in mpic_alloc()
1405 * also disable coreint if the MPIC node doesn't have in mpic_alloc()
1406 * an "fsl,mpic" compatible at all. This will be the case in mpic_alloc()
1415 /* When using a device-node, reset requests are only honored if the MPIC in mpic_alloc()
1418 if (!(mpic->flags & MPIC_NO_RESET)) { in mpic_alloc()
1419 printk(KERN_DEBUG "mpic: Resetting\n"); in mpic_alloc()
1420 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), in mpic_alloc()
1421 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) in mpic_alloc()
1423 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) in mpic_alloc()
1429 if (mpic->flags & MPIC_ENABLE_COREINT) in mpic_alloc()
1430 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), in mpic_alloc()
1431 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) in mpic_alloc()
1434 if (mpic->flags & MPIC_ENABLE_MCK) in mpic_alloc()
1435 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), in mpic_alloc()
1436 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) in mpic_alloc()
1440 * The MPIC driver will crash if there are more cores than we in mpic_alloc()
1445 /* Map the per-CPU registers */ in mpic_alloc()
1449 mpic_map(mpic, mpic->paddr, &mpic->cpuregs[cpu], in mpic_alloc()
1455 * Read feature register. For non-ISU MPICs, num sources as well. On in mpic_alloc()
1458 greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0)); in mpic_alloc()
1461 * By default, the last source number comes from the MPIC, but the in mpic_alloc()
1462 * device-tree and board support code can override it on buggy hw. in mpic_alloc()
1463 * If we get passed an isu_size (multi-isu MPIC) then we use that in mpic_alloc()
1469 last_irq = isu_size * MPIC_MAX_ISU - 1; in mpic_alloc()
1470 of_property_read_u32(mpic->node, "last-interrupt-source", &last_irq); in mpic_alloc()
1472 last_irq = irq_count - 1; in mpic_alloc()
1477 mpic->num_sources = isu_size; in mpic_alloc()
1478 mpic_map(mpic, mpic->paddr, &mpic->isus[0], in mpic_alloc()
1483 mpic->isu_size = isu_size; in mpic_alloc()
1484 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1); in mpic_alloc()
1485 mpic->isu_mask = (1 << mpic->isu_shift) - 1; in mpic_alloc()
1487 mpic->irqhost = irq_domain_create_linear(of_fwnode_handle(mpic->node), in mpic_alloc()
1489 &mpic_host_ops, mpic); in mpic_alloc()
1492 * FIXME: The code leaks the MPIC object and mappings here; this in mpic_alloc()
1495 if (mpic->irqhost == NULL) in mpic_alloc()
1513 printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx," in mpic_alloc()
1515 name, vers, (unsigned long long)mpic->paddr, num_possible_cpus()); in mpic_alloc()
1516 printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n", in mpic_alloc()
1517 mpic->isu_size, mpic->isu_shift, mpic->isu_mask); in mpic_alloc()
1519 mpic->next = mpics; in mpic_alloc()
1520 mpics = mpic; in mpic_alloc()
1522 if (!(mpic->flags & MPIC_SECONDARY)) { in mpic_alloc()
1523 mpic_primary = mpic; in mpic_alloc()
1524 irq_set_default_domain(mpic->irqhost); in mpic_alloc()
1527 return mpic; in mpic_alloc()
1534 void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num, in mpic_assign_isu() argument
1537 unsigned int isu_first = isu_num * mpic->isu_size; in mpic_assign_isu()
1541 mpic_map(mpic, in mpic_assign_isu()
1542 paddr, &mpic->isus[isu_num], 0, in mpic_assign_isu()
1543 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size); in mpic_assign_isu()
1545 if ((isu_first + mpic->isu_size) > mpic->num_sources) in mpic_assign_isu()
1546 mpic->num_sources = isu_first + mpic->isu_size; in mpic_assign_isu()
1549 void __init mpic_init(struct mpic *mpic) in mpic_init() argument
1554 BUG_ON(mpic->num_sources == 0); in mpic_init()
1556 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources); in mpic_init()
1561 if (mpic->flags & MPIC_FSL) { in mpic_init()
1562 u32 version = fsl_mpic_get_version(mpic); in mpic_init()
1565 * Timer group B is present at the latest in MPIC 3.1 (e.g. in mpic_init()
1566 * mpc8536). It is not present in MPIC 2.0 (e.g. mpc8544). in mpic_init()
1576 unsigned int offset = mpic_tm_offset(mpic, i); in mpic_init()
1578 mpic_write(mpic->tmregs, in mpic_init()
1581 mpic_write(mpic->tmregs, in mpic_init()
1585 (mpic->timer_vecs[0] + i)); in mpic_init()
1589 mpic_test_broken_ipi(mpic); in mpic_init()
1594 (mpic->ipi_vecs[0] + i)); in mpic_init()
1597 /* Do the HT PIC fixups on U3 broken mpic */ in mpic_init()
1598 DBG("MPIC flags: %x\n", mpic->flags); in mpic_init()
1599 if ((mpic->flags & MPIC_U3_HT_IRQS) && !(mpic->flags & MPIC_SECONDARY)) { in mpic_init()
1600 mpic_scan_ht_pics(mpic); in mpic_init()
1601 mpic_u3msi_init(mpic); in mpic_init()
1604 mpic_pasemi_msi_init(mpic); in mpic_init()
1606 cpu = mpic_processor_id(mpic); in mpic_init()
1608 if (!(mpic->flags & MPIC_NO_RESET)) { in mpic_init()
1609 for (i = 0; i < mpic->num_sources; i++) { in mpic_init()
1615 if (mpic->protected && test_bit(i, mpic->protected)) in mpic_init()
1624 mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec); in mpic_init()
1627 if (!(mpic->flags & MPIC_NO_PTHROU_DIS)) in mpic_init()
1628 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), in mpic_init()
1629 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) in mpic_init()
1632 if (mpic->flags & MPIC_NO_BIAS) in mpic_init()
1633 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), in mpic_init()
1634 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) in mpic_init()
1641 /* allocate memory to save mpic state */ in mpic_init()
1642 mpic->save_data = kmalloc_array(mpic->num_sources, in mpic_init()
1643 sizeof(*mpic->save_data), in mpic_init()
1645 BUG_ON(mpic->save_data == NULL); in mpic_init()
1648 /* Check if this MPIC is chained from a parent interrupt controller */ in mpic_init()
1649 if (mpic->flags & MPIC_SECONDARY) { in mpic_init()
1650 int virq = irq_of_parse_and_map(mpic->node, 0); in mpic_init()
1653 mpic->node, virq); in mpic_init()
1654 irq_set_handler_data(virq, mpic); in mpic_init()
1659 /* FSL mpic error interrupt initialization */ in mpic_init()
1660 if (mpic->flags & MPIC_FSL_HAS_EIMR) in mpic_init()
1661 mpic_err_int_init(mpic, MPIC_FSL_ERR_INT); in mpic_init()
1666 struct mpic *mpic = mpic_find(irq); in mpic_irq_set_priority() local
1671 if (!mpic) in mpic_irq_set_priority()
1675 if (mpic_is_ipi(mpic, src)) { in mpic_irq_set_priority()
1676 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) & in mpic_irq_set_priority()
1678 mpic_ipi_write(src - mpic->ipi_vecs[0], in mpic_irq_set_priority()
1680 } else if (mpic_is_tm(mpic, src)) { in mpic_irq_set_priority()
1681 reg = mpic_tm_read(src - mpic->timer_vecs[0]) & in mpic_irq_set_priority()
1683 mpic_tm_write(src - mpic->timer_vecs[0], in mpic_irq_set_priority()
1697 struct mpic *mpic = mpic_primary; in mpic_setup_this_cpu() local
1702 BUG_ON(mpic == NULL); in mpic_setup_this_cpu()
1704 DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); in mpic_setup_this_cpu()
1708 /* let the mpic know we want intrs. default affinity is 0xffffffff in mpic_setup_this_cpu()
1713 if (distribute_irqs && !(mpic->flags & MPIC_SINGLE_DEST_CPU)) { in mpic_setup_this_cpu()
1714 for (i = 0; i < mpic->num_sources ; i++) in mpic_setup_this_cpu()
1728 struct mpic *mpic = mpic_primary; in mpic_cpu_get_priority() local
1735 struct mpic *mpic = mpic_primary; in mpic_cpu_set_priority() local
1743 struct mpic *mpic = mpic_primary; in mpic_teardown_this_cpu() local
1748 BUG_ON(mpic == NULL); in mpic_teardown_this_cpu()
1750 DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id()); in mpic_teardown_this_cpu()
1753 /* let the mpic know we don't want intrs. */ in mpic_teardown_this_cpu()
1754 for (i = 0; i < mpic->num_sources ; i++) in mpic_teardown_this_cpu()
1760 /* We need to EOI the IPI since not all platforms reset the MPIC in mpic_teardown_this_cpu()
1763 mpic_eoi(mpic); in mpic_teardown_this_cpu()
1769 static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg) in _mpic_get_one_irq() argument
1775 DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src); in _mpic_get_one_irq()
1777 if (unlikely(src == mpic->spurious_vec)) { in _mpic_get_one_irq()
1778 if (mpic->flags & MPIC_SPV_EOI) in _mpic_get_one_irq()
1779 mpic_eoi(mpic); in _mpic_get_one_irq()
1782 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) { in _mpic_get_one_irq()
1784 mpic->name, (int)src); in _mpic_get_one_irq()
1785 mpic_eoi(mpic); in _mpic_get_one_irq()
1789 return irq_find_mapping(mpic->irqhost, src); in _mpic_get_one_irq()
1792 unsigned int mpic_get_one_irq(struct mpic *mpic) in mpic_get_one_irq() argument
1794 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK)); in mpic_get_one_irq()
1799 struct mpic *mpic = mpic_primary; in mpic_get_irq() local
1801 BUG_ON(mpic == NULL); in mpic_get_irq()
1803 return mpic_get_one_irq(mpic); in mpic_get_irq()
1809 struct mpic *mpic = mpic_primary; in mpic_get_coreint_irq() local
1812 BUG_ON(mpic == NULL); in mpic_get_coreint_irq()
1816 if (unlikely(src == mpic->spurious_vec)) { in mpic_get_coreint_irq()
1817 if (mpic->flags & MPIC_SPV_EOI) in mpic_get_coreint_irq()
1818 mpic_eoi(mpic); in mpic_get_coreint_irq()
1821 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) { in mpic_get_coreint_irq()
1823 mpic->name, (int)src); in mpic_get_coreint_irq()
1827 return irq_find_mapping(mpic->irqhost, src); in mpic_get_coreint_irq()
1835 struct mpic *mpic = mpic_primary; in mpic_get_mcirq() local
1837 BUG_ON(mpic == NULL); in mpic_get_mcirq()
1839 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK)); in mpic_get_mcirq()
1845 struct mpic *mpic = mpic_primary; in mpic_request_ipis() local
1847 BUG_ON(mpic == NULL); in mpic_request_ipis()
1849 printk(KERN_INFO "mpic: requesting IPIs...\n"); in mpic_request_ipis()
1852 unsigned int vipi = irq_create_mapping(mpic->irqhost, in mpic_request_ipis()
1853 mpic->ipi_vecs[0] + i); in mpic_request_ipis()
1864 struct mpic *mpic = mpic_primary; in smp_mpic_message_pass() local
1867 BUG_ON(mpic == NULL); in smp_mpic_message_pass()
1877 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, msg); in smp_mpic_message_pass()
1907 struct mpic *mpic = mpic_primary; in mpic_reset_core() local
1913 pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT)); in mpic_reset_core()
1915 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir); in mpic_reset_core()
1916 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT)); in mpic_reset_core()
1920 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir); in mpic_reset_core()
1921 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT)); in mpic_reset_core()
1925 if (mpic->flags & MPIC_FSL) { in mpic_reset_core()
1927 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpuid], in mpic_reset_core()
1935 static void mpic_suspend_one(struct mpic *mpic) in mpic_suspend_one() argument
1939 for (i = 0; i < mpic->num_sources; i++) { in mpic_suspend_one()
1940 mpic->save_data[i].vecprio = in mpic_suspend_one()
1942 mpic->save_data[i].dest = in mpic_suspend_one()
1949 struct mpic *mpic = mpics; in mpic_suspend() local
1951 while (mpic) { in mpic_suspend()
1952 mpic_suspend_one(mpic); in mpic_suspend()
1953 mpic = mpic->next; in mpic_suspend()
1959 static void mpic_resume_one(struct mpic *mpic) in mpic_resume_one() argument
1963 for (i = 0; i < mpic->num_sources; i++) { in mpic_resume_one()
1965 mpic->save_data[i].vecprio); in mpic_resume_one()
1967 mpic->save_data[i].dest); in mpic_resume_one()
1970 if (mpic->fixups) { in mpic_resume_one()
1971 struct mpic_irq_fixup *fixup = &mpic->fixups[i]; in mpic_resume_one()
1973 if (fixup->base) { in mpic_resume_one()
1975 if ((mpic->save_data[i].fixup_data & 1) == 0) in mpic_resume_one()
1979 writeb(0x10 + 2 * fixup->index, fixup->base + 2); in mpic_resume_one()
1981 writel(mpic->save_data[i].fixup_data & ~1, in mpic_resume_one()
1982 fixup->base + 4); in mpic_resume_one()
1991 struct mpic *mpic = mpics; in mpic_resume() local
1993 while (mpic) { in mpic_resume()
1994 mpic_resume_one(mpic); in mpic_resume()
1995 mpic = mpic->next; in mpic_resume()
2012 pr_err("mpic: Failed to register subsystem!\n"); in mpic_init_sys()