Lines Matching +full:port +full:- +full:phys
1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * - fixed maintenance access routines, check for aligned access
11 * - Added Port-Write message handling
12 * - Added Machine Check exception handling
16 * Lian Minghuan-B31939 <Minghuan.Lian@freescale.com>
24 #include <linux/dma-mapping.h>
33 (((struct rio_priv *)(mport->priv))->rmm_handle)
35 /* RapidIO definition irq, which read from OF-tree */
36 #define IRQ_RIO_PW(m) (((struct fsl_rio_pw *)(m))->pwirq)
37 #define IRQ_RIO_BELL(m) (((struct fsl_rio_dbell *)(m))->bellirq)
38 #define IRQ_RIO_TX(m) (((struct fsl_rmu *)(GET_RMM_HANDLE(m)))->txirq)
39 #define IRQ_RIO_RX(m) (((struct fsl_rmu *)(GET_RMM_HANDLE(m)))->rxirq)
164 dma_addr_t phys; member
174 dma_addr_t phys; member
197 * fsl_rio_tx_handler - MPC85xx outbound message interrupt handler
199 * @dev_instance: Pointer to interrupt-specific data
208 struct rio_mport *port = (struct rio_mport *)dev_instance; in fsl_rio_tx_handler() local
209 struct fsl_rmu *rmu = GET_RMM_HANDLE(port); in fsl_rio_tx_handler()
211 osr = in_be32(&rmu->msg_regs->osr); in fsl_rio_tx_handler()
215 out_be32(&rmu->msg_regs->osr, RIO_MSG_OSR_TE); in fsl_rio_tx_handler()
221 out_be32(&rmu->msg_regs->osr, RIO_MSG_OSR_QOI); in fsl_rio_tx_handler()
226 u32 dqp = in_be32(&rmu->msg_regs->odqdpar); in fsl_rio_tx_handler()
227 int slot = (dqp - rmu->msg_tx_ring.phys) >> 5; in fsl_rio_tx_handler()
228 if (port->outb_msg[0].mcback != NULL) { in fsl_rio_tx_handler()
229 port->outb_msg[0].mcback(port, rmu->msg_tx_ring.dev_id, in fsl_rio_tx_handler()
230 -1, in fsl_rio_tx_handler()
233 /* Ack the end-of-message interrupt */ in fsl_rio_tx_handler()
234 out_be32(&rmu->msg_regs->osr, RIO_MSG_OSR_EOMI); in fsl_rio_tx_handler()
242 * fsl_rio_rx_handler - MPC85xx inbound message interrupt handler
244 * @dev_instance: Pointer to interrupt-specific data
253 struct rio_mport *port = (struct rio_mport *)dev_instance; in fsl_rio_rx_handler() local
254 struct fsl_rmu *rmu = GET_RMM_HANDLE(port); in fsl_rio_rx_handler()
256 isr = in_be32(&rmu->msg_regs->isr); in fsl_rio_rx_handler()
260 out_be32((void *)&rmu->msg_regs->isr, RIO_MSG_ISR_TE); in fsl_rio_rx_handler()
271 if (port->inb_msg[0].mcback != NULL) in fsl_rio_rx_handler()
272 port->inb_msg[0].mcback(port, rmu->msg_rx_ring.dev_id, in fsl_rio_rx_handler()
273 -1, in fsl_rio_rx_handler()
274 -1); in fsl_rio_rx_handler()
277 out_be32(&rmu->msg_regs->isr, RIO_MSG_ISR_DIQI); in fsl_rio_rx_handler()
285 * fsl_rio_dbell_handler - MPC85xx doorbell interrupt handler
287 * @dev_instance: Pointer to interrupt-specific data
299 dsr = in_be32(&fsl_dbell->dbell_regs->dsr); in fsl_rio_dbell_handler()
303 out_be32(&fsl_dbell->dbell_regs->dsr, DOORBELL_DSR_TE); in fsl_rio_dbell_handler()
309 out_be32(&fsl_dbell->dbell_regs->dsr, DOORBELL_DSR_QFI); in fsl_rio_dbell_handler()
315 fsl_dbell->dbell_ring.virt + in fsl_rio_dbell_handler()
316 (in_be32(&fsl_dbell->dbell_regs->dqdpar) & 0xfff); in fsl_rio_dbell_handler()
323 dmsg->sid, dmsg->tid, dmsg->info); in fsl_rio_dbell_handler()
326 if (fsl_dbell->mport[i]) { in fsl_rio_dbell_handler()
328 &fsl_dbell->mport[i]->dbells, node) { in fsl_rio_dbell_handler()
329 if ((dbell->res->start in fsl_rio_dbell_handler()
330 <= dmsg->info) in fsl_rio_dbell_handler()
331 && (dbell->res->end in fsl_rio_dbell_handler()
332 >= dmsg->info)) { in fsl_rio_dbell_handler()
337 if (found && dbell->dinb) { in fsl_rio_dbell_handler()
338 dbell->dinb(fsl_dbell->mport[i], in fsl_rio_dbell_handler()
339 dbell->dev_id, dmsg->sid, in fsl_rio_dbell_handler()
340 dmsg->tid, in fsl_rio_dbell_handler()
341 dmsg->info); in fsl_rio_dbell_handler()
351 dmsg->sid, dmsg->tid, in fsl_rio_dbell_handler()
352 dmsg->info); in fsl_rio_dbell_handler()
354 setbits32(&fsl_dbell->dbell_regs->dmr, DOORBELL_DMR_DI); in fsl_rio_dbell_handler()
355 out_be32(&fsl_dbell->dbell_regs->dsr, DOORBELL_DSR_DIQI); in fsl_rio_dbell_handler()
373 out_be32(&dbell->dbell_regs->odsr, ODSR_CLEAR); in msg_unit_error_handler()
374 out_be32(&dbell->dbell_regs->dsr, IDSR_CLEAR); in msg_unit_error_handler()
376 out_be32(&pw->pw_regs->pwsr, IPWSR_CLEAR); in msg_unit_error_handler()
380 * fsl_rio_port_write_handler - MPC85xx port write interrupt handler
382 * @dev_instance: Pointer to interrupt-specific data
384 * Handles port write interrupts. Parses a list of registered
385 * port write event handlers and executes a matching event handler.
398 ipwmr = in_be32(&pw->pw_regs->pwmr); in fsl_rio_port_write_handler()
399 ipwsr = in_be32(&pw->pw_regs->pwsr); in fsl_rio_port_write_handler()
402 pr_debug("PW Int->IPWMR: 0x%08x IPWSR: 0x%08x (", ipwmr, ipwsr); in fsl_rio_port_write_handler()
420 if (kfifo_avail(&pw->pw_fifo) >= RIO_PW_MSG_SIZE) { in fsl_rio_port_write_handler()
421 pw->port_write_msg.msg_count++; in fsl_rio_port_write_handler()
422 kfifo_in(&pw->pw_fifo, pw->port_write_msg.virt, in fsl_rio_port_write_handler()
425 pw->port_write_msg.discard_count++; in fsl_rio_port_write_handler()
426 pr_debug("RIO: ISR Discarded Port-Write Msg(s) (%d)\n", in fsl_rio_port_write_handler()
427 pw->port_write_msg.discard_count); in fsl_rio_port_write_handler()
430 * another port-write to be received. in fsl_rio_port_write_handler()
432 out_be32(&pw->pw_regs->pwsr, RIO_IPWSR_QFI); in fsl_rio_port_write_handler()
433 out_be32(&pw->pw_regs->pwmr, ipwmr | RIO_IPWMR_CQ); in fsl_rio_port_write_handler()
435 schedule_work(&pw->pw_work); in fsl_rio_port_write_handler()
439 pw->port_write_msg.err_count++; in fsl_rio_port_write_handler()
440 pr_debug("RIO: Port-Write Transaction Err (%d)\n", in fsl_rio_port_write_handler()
441 pw->port_write_msg.err_count); in fsl_rio_port_write_handler()
442 /* Clear Transaction Error: port-write controller should be in fsl_rio_port_write_handler()
445 out_be32(&pw->pw_regs->pwmr, ipwmr & ~RIO_IPWMR_PWE); in fsl_rio_port_write_handler()
446 out_be32(&pw->pw_regs->pwsr, RIO_IPWSR_TE); in fsl_rio_port_write_handler()
447 out_be32(&pw->pw_regs->pwmr, ipwmr); in fsl_rio_port_write_handler()
451 pw->port_write_msg.discard_count++; in fsl_rio_port_write_handler()
452 pr_debug("RIO: Port Discarded Port-Write Msg(s) (%d)\n", in fsl_rio_port_write_handler()
453 pw->port_write_msg.discard_count); in fsl_rio_port_write_handler()
454 out_be32(&pw->pw_regs->pwsr, RIO_IPWSR_PWD); in fsl_rio_port_write_handler()
486 * Process port-write messages in fsl_pw_dpc()
488 while (kfifo_out_spinlocked(&pw->pw_fifo, (unsigned char *)&msg_buffer, in fsl_pw_dpc()
489 RIO_PW_MSG_SIZE, &pw->pw_fifo_lock)) { in fsl_pw_dpc()
493 pr_debug("%s : Port-Write Message:", __func__); in fsl_pw_dpc()
504 /* Pass the port-write message to RIO core for processing */ in fsl_pw_dpc()
506 if (pw->mport[i]) in fsl_pw_dpc()
507 rio_inb_pwrite_handler(pw->mport[i], in fsl_pw_dpc()
514 * fsl_rio_pw_enable - enable/disable port-write interface init
515 * @mport: Master port implementing the port write unit
516 * @enable: 1=enable; 0=disable port-write message handling
522 rval = in_be32(&pw->pw_regs->pwmr); in fsl_rio_pw_enable()
529 out_be32(&pw->pw_regs->pwmr, rval); in fsl_rio_pw_enable()
535 * fsl_rio_port_write_init - MPC85xx port write interface init
536 * @mport: Master port implementing the port write unit
538 * Initializes port write unit hardware and DMA buffer
540 * or %-ENOMEM on failure.
547 /* Following configurations require a disabled port write controller */ in fsl_rio_port_write_init()
548 out_be32(&pw->pw_regs->pwmr, in fsl_rio_port_write_init()
549 in_be32(&pw->pw_regs->pwmr) & ~RIO_IPWMR_PWE); in fsl_rio_port_write_init()
551 /* Initialize port write */ in fsl_rio_port_write_init()
552 pw->port_write_msg.virt = dma_alloc_coherent(pw->dev, in fsl_rio_port_write_init()
554 &pw->port_write_msg.phys, GFP_KERNEL); in fsl_rio_port_write_init()
555 if (!pw->port_write_msg.virt) { in fsl_rio_port_write_init()
556 pr_err("RIO: unable allocate port write queue\n"); in fsl_rio_port_write_init()
557 return -ENOMEM; in fsl_rio_port_write_init()
560 pw->port_write_msg.err_count = 0; in fsl_rio_port_write_init()
561 pw->port_write_msg.discard_count = 0; in fsl_rio_port_write_init()
564 out_be32(&pw->pw_regs->epwqbar, 0); in fsl_rio_port_write_init()
565 out_be32(&pw->pw_regs->pwqbar, (u32) pw->port_write_msg.phys); in fsl_rio_port_write_init()
568 in_be32(&pw->pw_regs->epwqbar), in fsl_rio_port_write_init()
569 in_be32(&pw->pw_regs->pwqbar)); in fsl_rio_port_write_init()
572 out_be32(&pw->pw_regs->pwsr, in fsl_rio_port_write_init()
575 /* Configure port write controller for snooping enable all reporting, in fsl_rio_port_write_init()
577 out_be32(&pw->pw_regs->pwmr, in fsl_rio_port_write_init()
581 /* Hook up port-write handler */ in fsl_rio_port_write_init()
583 IRQF_SHARED, "port-write", (void *)pw); in fsl_rio_port_write_init()
591 INIT_WORK(&pw->pw_work, fsl_pw_dpc); in fsl_rio_port_write_init()
592 spin_lock_init(&pw->pw_fifo_lock); in fsl_rio_port_write_init()
593 if (kfifo_alloc(&pw->pw_fifo, RIO_PW_MSG_SIZE * 32, GFP_KERNEL)) { in fsl_rio_port_write_init()
595 rc = -ENOMEM; in fsl_rio_port_write_init()
600 in_be32(&pw->pw_regs->pwmr), in fsl_rio_port_write_init()
601 in_be32(&pw->pw_regs->pwsr)); in fsl_rio_port_write_init()
608 dma_free_coherent(pw->dev, RIO_PW_MSG_SIZE, in fsl_rio_port_write_init()
609 pw->port_write_msg.virt, in fsl_rio_port_write_init()
610 pw->port_write_msg.phys); in fsl_rio_port_write_init()
615 * fsl_rio_doorbell_send - Send a MPC85xx doorbell message
616 * @mport: RapidIO master port info
619 * @data: 16-bit info field of RapidIO doorbell message
622 * %-EINVAL on failure.
637 out_be32(&dbell->dbell_regs->odmr, 0x00000000); in fsl_rio_doorbell_send()
638 out_be32(&dbell->dbell_regs->odretcr, 0x00000004); in fsl_rio_doorbell_send()
639 out_be32(&dbell->dbell_regs->oddpr, destid << 16); in fsl_rio_doorbell_send()
640 out_be32(&dbell->dbell_regs->oddatr, (index << 20) | data); in fsl_rio_doorbell_send()
641 out_be32(&dbell->dbell_regs->odmr, 0x00000001); in fsl_rio_doorbell_send()
649 * fsl_add_outb_message - Add message to the MPC85xx outbound message queue
650 * @mport: Master port with outbound message queue
657 * %0 on success or %-EINVAL on failure.
665 struct rio_tx_desc *desc = (struct rio_tx_desc *)rmu->msg_tx_ring.virt in fsl_add_outb_message()
666 + rmu->msg_tx_ring.tx_slot; in fsl_add_outb_message()
670 "%p len %8.8zx\n", rdev->destid, mbox, buffer, len); in fsl_add_outb_message()
672 ret = -EINVAL; in fsl_add_outb_message()
677 memcpy(rmu->msg_tx_ring.virt_buffer[rmu->msg_tx_ring.tx_slot], buffer, in fsl_add_outb_message()
679 if (len < (RIO_MAX_MSG_SIZE - 4)) in fsl_add_outb_message()
680 memset(rmu->msg_tx_ring.virt_buffer[rmu->msg_tx_ring.tx_slot] in fsl_add_outb_message()
681 + len, 0, RIO_MAX_MSG_SIZE - len); in fsl_add_outb_message()
684 desc->dport = (rdev->destid << 16) | (mbox & 0x3); in fsl_add_outb_message()
687 desc->dattr = 0x28000000 | ((mport->index) << 20); in fsl_add_outb_message()
690 desc->dwcnt = is_power_of_2(len) ? len : 1 << get_bitmask_order(len); in fsl_add_outb_message()
693 desc->saddr = 0x00000004 in fsl_add_outb_message()
694 | rmu->msg_tx_ring.phys_buffer[rmu->msg_tx_ring.tx_slot]; in fsl_add_outb_message()
697 omr = in_be32(&rmu->msg_regs->omr); in fsl_add_outb_message()
698 out_be32(&rmu->msg_regs->omr, omr | RIO_MSG_OMR_MUI); in fsl_add_outb_message()
701 if (++rmu->msg_tx_ring.tx_slot == rmu->msg_tx_ring.size) in fsl_add_outb_message()
702 rmu->msg_tx_ring.tx_slot = 0; in fsl_add_outb_message()
709 * fsl_open_outb_mbox - Initialize MPC85xx outbound mailbox
710 * @mport: Master port implementing the outbound message unit
717 * %-EINVAL or %-ENOMEM on failure.
723 struct rio_priv *priv = mport->priv; in fsl_open_outb_mbox()
728 rc = -EINVAL; in fsl_open_outb_mbox()
733 rmu->msg_tx_ring.dev_id = dev_id; in fsl_open_outb_mbox()
734 rmu->msg_tx_ring.size = entries; in fsl_open_outb_mbox()
736 for (i = 0; i < rmu->msg_tx_ring.size; i++) { in fsl_open_outb_mbox()
737 rmu->msg_tx_ring.virt_buffer[i] = in fsl_open_outb_mbox()
738 dma_alloc_coherent(priv->dev, RIO_MSG_BUFFER_SIZE, in fsl_open_outb_mbox()
739 &rmu->msg_tx_ring.phys_buffer[i], GFP_KERNEL); in fsl_open_outb_mbox()
740 if (!rmu->msg_tx_ring.virt_buffer[i]) { in fsl_open_outb_mbox()
741 rc = -ENOMEM; in fsl_open_outb_mbox()
742 for (j = 0; j < rmu->msg_tx_ring.size; j++) in fsl_open_outb_mbox()
743 if (rmu->msg_tx_ring.virt_buffer[j]) in fsl_open_outb_mbox()
744 dma_free_coherent(priv->dev, in fsl_open_outb_mbox()
746 rmu->msg_tx_ring. in fsl_open_outb_mbox()
748 rmu->msg_tx_ring. in fsl_open_outb_mbox()
755 rmu->msg_tx_ring.virt = dma_alloc_coherent(priv->dev, in fsl_open_outb_mbox()
756 rmu->msg_tx_ring.size * RIO_MSG_DESC_SIZE, in fsl_open_outb_mbox()
757 &rmu->msg_tx_ring.phys, in fsl_open_outb_mbox()
759 if (!rmu->msg_tx_ring.virt) { in fsl_open_outb_mbox()
760 rc = -ENOMEM; in fsl_open_outb_mbox()
763 rmu->msg_tx_ring.tx_slot = 0; in fsl_open_outb_mbox()
766 out_be32(&rmu->msg_regs->odqdpar, rmu->msg_tx_ring.phys); in fsl_open_outb_mbox()
767 out_be32(&rmu->msg_regs->odqepar, rmu->msg_tx_ring.phys); in fsl_open_outb_mbox()
770 out_be32(&rmu->msg_regs->osar, 0x00000004); in fsl_open_outb_mbox()
773 out_be32(&rmu->msg_regs->osr, 0x000000b3); in fsl_open_outb_mbox()
788 out_be32(&rmu->msg_regs->omr, 0x00100220); in fsl_open_outb_mbox()
791 out_be32(&rmu->msg_regs->omr, in fsl_open_outb_mbox()
792 in_be32(&rmu->msg_regs->omr) | in fsl_open_outb_mbox()
793 ((get_bitmask_order(entries) - 2) << 12)); in fsl_open_outb_mbox()
796 out_be32(&rmu->msg_regs->omr, in_be32(&rmu->msg_regs->omr) | 0x1); in fsl_open_outb_mbox()
802 dma_free_coherent(priv->dev, in fsl_open_outb_mbox()
803 rmu->msg_tx_ring.size * RIO_MSG_DESC_SIZE, in fsl_open_outb_mbox()
804 rmu->msg_tx_ring.virt, rmu->msg_tx_ring.phys); in fsl_open_outb_mbox()
807 for (i = 0; i < rmu->msg_tx_ring.size; i++) in fsl_open_outb_mbox()
808 dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE, in fsl_open_outb_mbox()
809 rmu->msg_tx_ring.virt_buffer[i], in fsl_open_outb_mbox()
810 rmu->msg_tx_ring.phys_buffer[i]); in fsl_open_outb_mbox()
816 * fsl_close_outb_mbox - Shut down MPC85xx outbound mailbox
817 * @mport: Master port implementing the outbound message unit
825 struct rio_priv *priv = mport->priv; in fsl_close_outb_mbox()
829 out_be32(&rmu->msg_regs->omr, 0); in fsl_close_outb_mbox()
832 dma_free_coherent(priv->dev, in fsl_close_outb_mbox()
833 rmu->msg_tx_ring.size * RIO_MSG_DESC_SIZE, in fsl_close_outb_mbox()
834 rmu->msg_tx_ring.virt, rmu->msg_tx_ring.phys); in fsl_close_outb_mbox()
841 * fsl_open_inb_mbox - Initialize MPC85xx inbound mailbox
842 * @mport: Master port implementing the inbound message unit
849 * and %-EINVAL or %-ENOMEM on failure.
855 struct rio_priv *priv = mport->priv; in fsl_open_inb_mbox()
860 rc = -EINVAL; in fsl_open_inb_mbox()
865 rmu->msg_rx_ring.dev_id = dev_id; in fsl_open_inb_mbox()
866 rmu->msg_rx_ring.size = entries; in fsl_open_inb_mbox()
867 rmu->msg_rx_ring.rx_slot = 0; in fsl_open_inb_mbox()
868 for (i = 0; i < rmu->msg_rx_ring.size; i++) in fsl_open_inb_mbox()
869 rmu->msg_rx_ring.virt_buffer[i] = NULL; in fsl_open_inb_mbox()
872 rmu->msg_rx_ring.virt = dma_alloc_coherent(priv->dev, in fsl_open_inb_mbox()
873 rmu->msg_rx_ring.size * RIO_MAX_MSG_SIZE, in fsl_open_inb_mbox()
874 &rmu->msg_rx_ring.phys, GFP_KERNEL); in fsl_open_inb_mbox()
875 if (!rmu->msg_rx_ring.virt) { in fsl_open_inb_mbox()
876 rc = -ENOMEM; in fsl_open_inb_mbox()
881 out_be32(&rmu->msg_regs->ifqdpar, (u32) rmu->msg_rx_ring.phys); in fsl_open_inb_mbox()
882 out_be32(&rmu->msg_regs->ifqepar, (u32) rmu->msg_rx_ring.phys); in fsl_open_inb_mbox()
885 out_be32(&rmu->msg_regs->isr, 0x00000091); in fsl_open_inb_mbox()
891 dma_free_coherent(priv->dev, in fsl_open_inb_mbox()
892 rmu->msg_rx_ring.size * RIO_MAX_MSG_SIZE, in fsl_open_inb_mbox()
893 rmu->msg_rx_ring.virt, rmu->msg_rx_ring.phys); in fsl_open_inb_mbox()
904 out_be32(&rmu->msg_regs->imr, 0x001b0060); in fsl_open_inb_mbox()
907 setbits32(&rmu->msg_regs->imr, (get_bitmask_order(entries) - 2) << 12); in fsl_open_inb_mbox()
910 setbits32(&rmu->msg_regs->imr, 0x1); in fsl_open_inb_mbox()
917 * fsl_close_inb_mbox - Shut down MPC85xx inbound mailbox
918 * @mport: Master port implementing the inbound message unit
926 struct rio_priv *priv = mport->priv; in fsl_close_inb_mbox()
930 out_be32(&rmu->msg_regs->imr, 0); in fsl_close_inb_mbox()
933 dma_free_coherent(priv->dev, rmu->msg_rx_ring.size * RIO_MAX_MSG_SIZE, in fsl_close_inb_mbox()
934 rmu->msg_rx_ring.virt, rmu->msg_rx_ring.phys); in fsl_close_inb_mbox()
941 * fsl_add_inb_buffer - Add buffer to the MPC85xx inbound message queue
942 * @mport: Master port implementing the inbound message unit
947 * %0 on success or %-EINVAL on failure.
955 rmu->msg_rx_ring.rx_slot); in fsl_add_inb_buffer()
957 if (rmu->msg_rx_ring.virt_buffer[rmu->msg_rx_ring.rx_slot]) { in fsl_add_inb_buffer()
960 rmu->msg_rx_ring.rx_slot); in fsl_add_inb_buffer()
961 rc = -EINVAL; in fsl_add_inb_buffer()
965 rmu->msg_rx_ring.virt_buffer[rmu->msg_rx_ring.rx_slot] = buf; in fsl_add_inb_buffer()
966 if (++rmu->msg_rx_ring.rx_slot == rmu->msg_rx_ring.size) in fsl_add_inb_buffer()
967 rmu->msg_rx_ring.rx_slot = 0; in fsl_add_inb_buffer()
974 * fsl_get_inb_message - Fetch inbound message from the MPC85xx message unit
975 * @mport: Master port implementing the inbound message unit
989 phys_buf = in_be32(&rmu->msg_regs->ifqdpar); in fsl_get_inb_message()
992 if (phys_buf == in_be32(&rmu->msg_regs->ifqepar)) in fsl_get_inb_message()
995 virt_buf = rmu->msg_rx_ring.virt + (phys_buf in fsl_get_inb_message()
996 - rmu->msg_rx_ring.phys); in fsl_get_inb_message()
997 buf_idx = (phys_buf - rmu->msg_rx_ring.phys) / RIO_MAX_MSG_SIZE; in fsl_get_inb_message()
998 buf = rmu->msg_rx_ring.virt_buffer[buf_idx]; in fsl_get_inb_message()
1010 rmu->msg_rx_ring.virt_buffer[buf_idx] = NULL; in fsl_get_inb_message()
1013 setbits32(&rmu->msg_regs->imr, RIO_MSG_IMR_MI); in fsl_get_inb_message()
1020 * fsl_rio_doorbell_init - MPC85xx doorbell interface init
1021 * @mport: Master port implementing the inbound doorbell unit
1025 * or %-ENOMEM on failure.
1032 dbell->dbell_ring.virt = dma_alloc_coherent(dbell->dev, 512 * in fsl_rio_doorbell_init()
1033 DOORBELL_MESSAGE_SIZE, &dbell->dbell_ring.phys, GFP_KERNEL); in fsl_rio_doorbell_init()
1034 if (!dbell->dbell_ring.virt) { in fsl_rio_doorbell_init()
1036 rc = -ENOMEM; in fsl_rio_doorbell_init()
1041 out_be32(&dbell->dbell_regs->dqdpar, (u32) dbell->dbell_ring.phys); in fsl_rio_doorbell_init()
1042 out_be32(&dbell->dbell_regs->dqepar, (u32) dbell->dbell_ring.phys); in fsl_rio_doorbell_init()
1045 out_be32(&dbell->dbell_regs->dsr, 0x00000091); in fsl_rio_doorbell_init()
1051 dma_free_coherent(dbell->dev, 512 * DOORBELL_MESSAGE_SIZE, in fsl_rio_doorbell_init()
1052 dbell->dbell_ring.virt, dbell->dbell_ring.phys); in fsl_rio_doorbell_init()
1059 out_be32(&dbell->dbell_regs->dmr, 0x00108161); in fsl_rio_doorbell_init()
1071 if (!mport || !mport->priv) in fsl_rio_setup_rmu()
1072 return -EINVAL; in fsl_rio_setup_rmu()
1074 priv = mport->priv; in fsl_rio_setup_rmu()
1077 dev_warn(priv->dev, "Can't get %pOF property 'fsl,rmu'\n", in fsl_rio_setup_rmu()
1078 priv->dev->of_node); in fsl_rio_setup_rmu()
1079 return -EINVAL; in fsl_rio_setup_rmu()
1084 return -ENOMEM; in fsl_rio_setup_rmu()
1087 pr_err("%pOF: unable to find 'reg' property of message-unit\n", in fsl_rio_setup_rmu()
1090 return -ENOMEM; in fsl_rio_setup_rmu()
1092 rmu->msg_regs = (struct rio_msg_regs *) in fsl_rio_setup_rmu()
1095 rmu->txirq = irq_of_parse_and_map(node, 0); in fsl_rio_setup_rmu()
1096 rmu->rxirq = irq_of_parse_and_map(node, 1); in fsl_rio_setup_rmu()
1098 node, rmu->txirq, rmu->rxirq); in fsl_rio_setup_rmu()
1100 priv->rmm_handle = rmu; in fsl_rio_setup_rmu()
1102 rio_init_dbell_res(&mport->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff); in fsl_rio_setup_rmu()
1103 rio_init_mbox_res(&mport->riores[RIO_INB_MBOX_RESOURCE], 0, 0); in fsl_rio_setup_rmu()
1104 rio_init_mbox_res(&mport->riores[RIO_OUTB_MBOX_RESOURCE], 0, 0); in fsl_rio_setup_rmu()