Lines Matching defs:ccsr_pci

59 struct ccsr_pci {  struct
60 	__be32	config_addr;		/* 0x.000 - PCI/PCIE Configuration Address Register */
61 	__be32	config_data;		/* 0x.004 - PCI/PCIE Configuration Data Register */
62 	__be32	int_ack;		/* 0x.008 - PCI Interrupt Acknowledge Register */
63 	__be32	pex_otb_cpl_tor;	/* 0x.00c - PCIE Outbound completion timeout register */
64 	__be32	pex_conf_tor;		/* 0x.010 - PCIE configuration timeout register */
65 	__be32	pex_config;		/* 0x.014 - PCIE CONFIG Register */
66 	__be32	pex_int_status;		/* 0x.018 - PCIE interrupt status */
67 	u8	res2[4];
68 	__be32	pex_pme_mes_dr;		/* 0x.020 - PCIE PME and message detect register */
69 	__be32	pex_pme_mes_disr;	/* 0x.024 - PCIE PME and message disable register */
70 	__be32	pex_pme_mes_ier;	/* 0x.028 - PCIE PME and message interrupt enable register */
71 	__be32	pex_pmcr;		/* 0x.02c - PCIE power management command register */
72 	u8	res3[3016];
73 	__be32	block_rev1;	/* 0x.bf8 - PCIE Block Revision register 1 */
74 	__be32	block_rev2;	/* 0x.bfc - PCIE Block Revision register 2 */
81 	struct pci_outbound_window_regs pow[5];
82 	u8	res14[96];
83 	struct pci_inbound_window_regs	pmit;	/* 0xd00 - 0xd9c Inbound MSI */
84 	u8	res6[96];
89 	struct pci_inbound_window_regs piw[4];
91 	__be32	pex_err_dr;		/* 0x.e00 - PCI/PCIE error detect register */
92 	u8	res21[4];
93 	__be32	pex_err_en;		/* 0x.e08 - PCI/PCIE error interrupt enable register */
94 	u8	res22[4];
95 	__be32	pex_err_disr;		/* 0x.e10 - PCI/PCIE error disable register */
96 	u8	res23[12];
97 	__be32	pex_err_cap_stat;	/* 0x.e20 - PCI/PCIE error capture status register */
98 	u8	res24[4];
99 	__be32	pex_err_cap_r0;		/* 0x.e28 - PCIE error capture register 0 */
100 	__be32	pex_err_cap_r1;		/* 0x.e2c - PCIE error capture register 0 */
101 	__be32	pex_err_cap_r2;		/* 0x.e30 - PCIE error capture register 0 */
102 	__be32	pex_err_cap_r3;		/* 0x.e34 - PCIE error capture register 0 */
103 	u8	res_e38[200];
104 	__be32	pdb_stat;		/* 0x.f00 - PCIE Debug Status */
105 	u8	res_f04[16];
106 	__be32	pex_csr0;		/* 0x.f14 - PEX Control/Status register 0*/
110 	__be32	pex_csr1;		/* 0x.f18 - PEX Control/Status register 1*/
111 	u8	res_f1c[228];