Lines Matching +full:pcie +full:- +full:mem
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MPC83xx/85xx/86xx PCI/PCIE support routing.
5 * Copyright 2007-2012 Freescale Semiconductor, Inc.
6 * Copyright 2008-2009 MontaVista Software, Inc.
11 * Roy Zang <tie-fei.zang@freescale.com>
12 * MPC83xx PCI-Express support:
34 #include <asm/pci-bridge.h>
35 #include <asm/ppc-pci.h>
39 #include <asm/ppc-opcode.h>
51 /* if we aren't a PCIe don't bother */ in quirk_fsl_pcie_early()
60 dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL; in quirk_fsl_pcie_early()
72 if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) { in fsl_pcie_check_link()
73 if (hose->ops->read == fsl_indirect_read_config) in fsl_pcie_check_link()
74 __indirect_read_config(hose, hose->first_busno, 0, in fsl_pcie_check_link()
81 struct ccsr_pci __iomem *pci = hose->private_data; in fsl_pcie_check_link()
82 /* for PCIe IP rev 3.0 or greater use CSR0 for link state */ in fsl_pcie_check_link()
83 val = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK) in fsl_pcie_check_link()
98 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; in fsl_indirect_read_config()
100 hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK; in fsl_indirect_read_config()
118 struct pci_controller *hose = pci_bus_to_host(pdev->bus); in pci_dma_dev_setup_swiotlb()
120 pdev->dev.bus_dma_limit = in pci_dma_dev_setup_swiotlb()
121 hose->dma_window_base_cur + hose->dma_window_size - 1; in pci_dma_dev_setup_swiotlb()
127 hose->controller_ops.dma_dev_setup = pci_dma_dev_setup_swiotlb; in setup_swiotlb_ops()
139 if (dev_is_pci(dev) && dma_mask >= pci64_dma_offset * 2 - 1) { in fsl_pci_dma_set_mask()
140 dev->bus_dma_limit = 0; in fsl_pci_dma_set_mask()
141 dev->archdata.dma_offset = pci64_dma_offset; in fsl_pci_dma_set_mask()
149 resource_size_t pci_addr = res->start - offset; in setup_one_atmu()
150 resource_size_t phys_addr = res->start; in setup_one_atmu()
152 u32 flags = 0x80044000; /* enable & mem R/W */ in setup_one_atmu()
155 pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n", in setup_one_atmu()
156 (u64)res->start, (u64)size); in setup_one_atmu()
158 if (res->flags & IORESOURCE_PREFETCH) in setup_one_atmu()
166 return -1; in setup_one_atmu()
168 out_be32(&pci->pow[index + i].potar, pci_addr >> 12); in setup_one_atmu()
169 out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44); in setup_one_atmu()
170 out_be32(&pci->pow[index + i].powbar, phys_addr >> 12); in setup_one_atmu()
171 out_be32(&pci->pow[index + i].powar, flags | (bits - 1)); in setup_one_atmu()
175 size -= (resource_size_t)1U << bits; in setup_one_atmu()
192 ret = of_property_read_bool(node, "linux,usable-memory"); in is_kdump()
198 /* atmu setup for fsl pci/pcie controller */
201 struct ccsr_pci __iomem *pci = hose->private_data; in setup_pci_atmu()
203 u64 mem, sz, paddr_hi = 0; in setup_pci_atmu() local
214 * errors by closing the window on in-flight DMA. in setup_pci_atmu()
217 * hose->dma_window_size still get set. in setup_pci_atmu()
221 if (of_device_is_compatible(hose->dn, "fsl,bsc9132-pcie")) { in setup_pci_atmu()
235 if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_2_2) { in setup_pci_atmu()
244 out_be32(&pci->pow[i].powar, 0); in setup_pci_atmu()
248 out_be32(&pci->piw[i].piwar, 0); in setup_pci_atmu()
251 /* Setup outbound MEM window */ in setup_pci_atmu()
253 if (!(hose->mem_resources[i].flags & IORESOURCE_MEM)) in setup_pci_atmu()
256 paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start); in setup_pci_atmu()
257 paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end); in setup_pci_atmu()
260 offset = hose->mem_offset[i]; in setup_pci_atmu()
261 n = setup_one_atmu(pci, j, &hose->mem_resources[i], offset); in setup_pci_atmu()
265 hose->mem_resources[i].flags |= IORESOURCE_DISABLED; in setup_pci_atmu()
271 if (hose->io_resource.flags & IORESOURCE_IO) { in setup_pci_atmu()
277 (u64)hose->io_resource.start, in setup_pci_atmu()
278 (u64)resource_size(&hose->io_resource), in setup_pci_atmu()
279 (u64)hose->io_base_phys); in setup_pci_atmu()
280 out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12)); in setup_pci_atmu()
281 out_be32(&pci->pow[j].potear, 0); in setup_pci_atmu()
282 out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12)); in setup_pci_atmu()
284 out_be32(&pci->pow[j].powar, 0x80088000 in setup_pci_atmu()
285 | (ilog2(hose->io_resource.end in setup_pci_atmu()
286 - hose->io_resource.start + 1) - 1)); in setup_pci_atmu()
291 paddr_hi -= offset; in setup_pci_atmu()
292 paddr_lo -= offset; in setup_pci_atmu()
295 pr_err("%pOF: No outbound window space\n", hose->dn); in setup_pci_atmu()
300 pr_err("%pOF: No space for inbound window\n", hose->dn); in setup_pci_atmu()
309 if (paddr_hi < (0x100000000ull - pcicsrbar_sz) || in setup_pci_atmu()
311 pcicsrbar = 0x100000000ull - pcicsrbar_sz; in setup_pci_atmu()
313 pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz; in setup_pci_atmu()
318 pr_info("%pOF: PCICSRBAR @ 0x%x\n", hose->dn, pcicsrbar); in setup_pci_atmu()
320 /* Setup inbound mem window */ in setup_pci_atmu()
321 mem = memblock_end_of_DRAM(); in setup_pci_atmu()
322 pr_info("%s: end of DRAM %llx\n", __func__, mem); in setup_pci_atmu()
325 * The msi-address-64 property, if it exists, indicates the physical in setup_pci_atmu()
336 reg = of_get_property(hose->dn, "msi-address-64", &len); in setup_pci_atmu()
340 if ((address >= mem) && (address < (mem + PAGE_SIZE))) { in setup_pci_atmu()
341 pr_info("%pOF: extending DDR ATMU to cover MSIIR", hose->dn); in setup_pci_atmu()
342 mem += PAGE_SIZE; in setup_pci_atmu()
345 pr_warn("%pOF: msi-address-64 address of %llx is " in setup_pci_atmu()
346 "unsupported\n", hose->dn, address); in setup_pci_atmu()
350 sz = min(mem, paddr_lo); in setup_pci_atmu()
353 /* PCIe can overmap inbound & outbound since RX & TX are separated */ in setup_pci_atmu()
355 /* Size window to exact size if power-of-two or one size up */ in setup_pci_atmu()
356 if ((1ull << mem_log) != mem) { in setup_pci_atmu()
358 if ((1ull << mem_log) > mem) in setup_pci_atmu()
360 "greater than memory size\n", hose->dn); in setup_pci_atmu()
363 piwar |= ((mem_log - 1) & PIWAR_SZ_MASK); in setup_pci_atmu()
367 out_be32(&pci->piw[win_idx].pitar, 0x00000000); in setup_pci_atmu()
368 out_be32(&pci->piw[win_idx].piwbar, 0x00000000); in setup_pci_atmu()
369 out_be32(&pci->piw[win_idx].piwar, piwar); in setup_pci_atmu()
372 win_idx--; in setup_pci_atmu()
373 hose->dma_window_base_cur = 0x00000000; in setup_pci_atmu()
374 hose->dma_window_size = (resource_size_t)sz; in setup_pci_atmu()
378 * let devices that are 64-bit address capable to work w/o in setup_pci_atmu()
381 if (sz != mem) { in setup_pci_atmu()
382 mem_log = ilog2(mem); in setup_pci_atmu()
384 /* Size window up if we dont fit in exact power-of-2 */ in setup_pci_atmu()
385 if ((1ull << mem_log) != mem) in setup_pci_atmu()
388 piwar = (piwar & ~PIWAR_SZ_MASK) | (mem_log - 1); in setup_pci_atmu()
393 out_be32(&pci->piw[win_idx].pitar, 0x00000000); in setup_pci_atmu()
394 out_be32(&pci->piw[win_idx].piwbear, in setup_pci_atmu()
396 out_be32(&pci->piw[win_idx].piwbar, in setup_pci_atmu()
398 out_be32(&pci->piw[win_idx].piwar, piwar); in setup_pci_atmu()
407 pr_info("%pOF: Setup 64-bit PCI DMA window\n", hose->dn); in setup_pci_atmu()
414 out_be32(&pci->piw[win_idx].pitar, paddr >> 12); in setup_pci_atmu()
415 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12); in setup_pci_atmu()
416 out_be32(&pci->piw[win_idx].piwar, in setup_pci_atmu()
417 (piwar | (mem_log - 1))); in setup_pci_atmu()
420 win_idx--; in setup_pci_atmu()
422 sz -= 1ull << mem_log; in setup_pci_atmu()
426 piwar |= (mem_log - 1); in setup_pci_atmu()
429 out_be32(&pci->piw[win_idx].pitar, in setup_pci_atmu()
431 out_be32(&pci->piw[win_idx].piwbar, in setup_pci_atmu()
433 out_be32(&pci->piw[win_idx].piwar, piwar); in setup_pci_atmu()
436 win_idx--; in setup_pci_atmu()
440 hose->dma_window_base_cur = 0x00000000; in setup_pci_atmu()
441 hose->dma_window_size = (resource_size_t)paddr; in setup_pci_atmu()
444 if (hose->dma_window_size < mem) { in setup_pci_atmu()
449 "map - enable CONFIG_SWIOTLB to avoid dma errors.\n", in setup_pci_atmu()
450 hose->dn); in setup_pci_atmu()
452 /* adjusting outbound windows could reclaim space in mem map */ in setup_pci_atmu()
457 hose->dn); in setup_pci_atmu()
459 pr_info("%pOF: DMA window size is 0x%llx\n", hose->dn, in setup_pci_atmu()
460 (u64)hose->dma_window_size); in setup_pci_atmu()
494 * has bus->resource[0..4] set, so things are a bit more in fsl_pcibios_fixup_bus()
500 no_link = !!(hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK); in fsl_pcibios_fixup_bus()
502 if (bus->parent == hose->bus && (is_pcie || no_link)) { in fsl_pcibios_fixup_bus()
504 struct resource *res = bus->resource[i]; in fsl_pcibios_fixup_bus()
510 par = &hose->io_resource; in fsl_pcibios_fixup_bus()
512 par = &hose->mem_resources[i-1]; in fsl_pcibios_fixup_bus()
515 res->start = par ? par->start : 0; in fsl_pcibios_fixup_bus()
516 res->end = par ? par->end : 0; in fsl_pcibios_fixup_bus()
517 res->flags = par ? par->flags : 0; in fsl_pcibios_fixup_bus()
535 dev = pdev->dev.of_node; in fsl_add_bridge()
539 return -ENODEV; in fsl_add_bridge()
547 return -ENOMEM; in fsl_add_bridge()
551 bus_range = of_get_property(dev, "bus-range", &len); in fsl_add_bridge()
553 printk(KERN_WARNING "Can't get bus-range for %pOF, assume" in fsl_add_bridge()
559 return -ENOMEM; in fsl_add_bridge()
562 hose->parent = &pdev->dev; in fsl_add_bridge()
563 hose->first_busno = bus_range ? bus_range[0] : 0x0; in fsl_add_bridge()
564 hose->last_busno = bus_range ? bus_range[1] : 0xff; in fsl_add_bridge()
569 pci = hose->private_data = ioremap(rsrc.start, resource_size(&rsrc)); in fsl_add_bridge()
570 if (!hose->private_data) in fsl_add_bridge()
576 if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0) in fsl_add_bridge()
577 hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK; in fsl_add_bridge()
580 /* use fsl_indirect_read_config for PCIe */ in fsl_add_bridge()
581 hose->ops = &fsl_indirect_pcie_ops; in fsl_add_bridge()
582 /* For PCIE read HEADER_TYPE to identify controller mode */ in fsl_add_bridge()
591 !of_property_read_bool(dev, "fsl,pci-agent-force-enum")) in fsl_add_bridge()
599 hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG | in fsl_add_bridge()
602 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; in fsl_add_bridge()
603 /* Fix Class Code to PCI_CLASS_BRIDGE_PCI_NORMAL for pre-3.0 controller */ in fsl_add_bridge()
604 if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0) { in fsl_add_bridge()
615 * PCI-X operation is not affected. in fsl_add_bridge()
634 "Firmware bus number: %d->%d\n", in fsl_add_bridge()
635 (unsigned long long)rsrc.start, hose->first_busno, in fsl_add_bridge()
636 hose->last_busno); in fsl_add_bridge()
638 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", in fsl_add_bridge()
639 hose, hose->cfg_addr, hose->cfg_data); in fsl_add_bridge()
654 iounmap(hose->private_data); in fsl_add_bridge()
656 if (((unsigned long)hose->cfg_data & PAGE_MASK) != in fsl_add_bridge()
657 ((unsigned long)hose->cfg_addr & PAGE_MASK)) in fsl_add_bridge()
658 iounmap(hose->cfg_data); in fsl_add_bridge()
659 iounmap(hose->cfg_addr); in fsl_add_bridge()
661 return -ENODEV; in fsl_add_bridge()
683 * With the convention of u-boot, the PCIE outbound window 0 serves
696 if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) in mpc83xx_pcie_exclude_device()
700 * PCI-E controller does not check the device number bits and just in mpc83xx_pcie_exclude_device()
703 if (bus->number == hose->first_busno || in mpc83xx_pcie_exclude_device()
704 bus->primary == hose->first_busno) { in mpc83xx_pcie_exclude_device()
710 if (ppc_md.pci_exclude_device(hose, bus->number, devfn)) in mpc83xx_pcie_exclude_device()
721 struct mpc83xx_pcie_priv *pcie = hose->dn->data; in mpc83xx_pcie_remap_cfg() local
722 u32 dev_base = bus->number << 24 | devfn << 16; in mpc83xx_pcie_remap_cfg()
732 if (bus->number == hose->first_busno) in mpc83xx_pcie_remap_cfg()
733 return pcie->cfg_type0 + offset; in mpc83xx_pcie_remap_cfg()
735 if (pcie->dev_base == dev_base) in mpc83xx_pcie_remap_cfg()
738 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base); in mpc83xx_pcie_remap_cfg()
740 pcie->dev_base = dev_base; in mpc83xx_pcie_remap_cfg()
742 return pcie->cfg_type1 + offset; in mpc83xx_pcie_remap_cfg()
751 if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno) in mpc83xx_pcie_write_config()
766 struct mpc83xx_pcie_priv *pcie; in mpc83xx_pcie_setup() local
768 int ret = -ENOMEM; in mpc83xx_pcie_setup()
770 pcie = kzalloc(sizeof(*pcie), GFP_KERNEL); in mpc83xx_pcie_setup()
771 if (!pcie) in mpc83xx_pcie_setup()
774 pcie->cfg_type0 = ioremap(reg->start, resource_size(reg)); in mpc83xx_pcie_setup()
775 if (!pcie->cfg_type0) in mpc83xx_pcie_setup()
778 cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR); in mpc83xx_pcie_setup()
780 /* PCI-E isn't configured. */ in mpc83xx_pcie_setup()
781 ret = -ENODEV; in mpc83xx_pcie_setup()
785 pcie->cfg_type1 = ioremap(cfg_bar, 0x1000); in mpc83xx_pcie_setup()
786 if (!pcie->cfg_type1) in mpc83xx_pcie_setup()
789 WARN_ON(hose->dn->data); in mpc83xx_pcie_setup()
790 hose->dn->data = pcie; in mpc83xx_pcie_setup()
791 hose->ops = &mpc83xx_pcie_ops; in mpc83xx_pcie_setup()
792 hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK; in mpc83xx_pcie_setup()
794 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0); in mpc83xx_pcie_setup()
795 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0); in mpc83xx_pcie_setup()
798 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; in mpc83xx_pcie_setup()
802 iounmap(pcie->cfg_type0); in mpc83xx_pcie_setup()
804 kfree(pcie); in mpc83xx_pcie_setup()
824 return -ENODEV; in mpc83xx_add_bridge()
831 return -ENOMEM; in mpc83xx_add_bridge()
859 bus_range = of_get_property(dev, "bus-range", &len); in mpc83xx_add_bridge()
861 printk(KERN_WARNING "Can't get bus-range for %pOF, assume" in mpc83xx_add_bridge()
868 return -ENOMEM; in mpc83xx_add_bridge()
870 hose->first_busno = bus_range ? bus_range[0] : 0; in mpc83xx_add_bridge()
871 hose->last_busno = bus_range ? bus_range[1] : 0xff; in mpc83xx_add_bridge()
873 if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) { in mpc83xx_add_bridge()
883 "Firmware bus number: %d->%d\n", in mpc83xx_add_bridge()
884 (unsigned long long)rsrc_reg.start, hose->first_busno, in mpc83xx_add_bridge()
885 hose->last_busno); in mpc83xx_add_bridge()
887 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", in mpc83xx_add_bridge()
888 hose, hose->cfg_addr, hose->cfg_data); in mpc83xx_add_bridge()
905 struct mpc83xx_pcie_priv *pcie = hose->dn->data; in fsl_pci_immrbar_base() local
910 in = pcie->cfg_type0 + PEX_RC_INWIN_BASE; in fsl_pci_immrbar_base()
929 pci_bus_read_config_dword(hose->bus, in fsl_pci_immrbar_base()
933 * For PEXCSRBAR, bit 3-0 indicate prefetchable and in fsl_pci_immrbar_base()
961 regs->gpr[rd] = 0xffffffff; in mcheck_handle_load()
965 regs->gpr[rd] = 0xffffffff; in mcheck_handle_load()
966 regs->gpr[ra] += regs->gpr[rb]; in mcheck_handle_load()
970 regs->gpr[rd] = 0xff; in mcheck_handle_load()
974 regs->gpr[rd] = 0xff; in mcheck_handle_load()
975 regs->gpr[ra] += regs->gpr[rb]; in mcheck_handle_load()
980 regs->gpr[rd] = 0xffff; in mcheck_handle_load()
984 regs->gpr[rd] = 0xffff; in mcheck_handle_load()
985 regs->gpr[ra] += regs->gpr[rb]; in mcheck_handle_load()
989 regs->gpr[rd] = ~0UL; in mcheck_handle_load()
993 regs->gpr[rd] = ~0UL; in mcheck_handle_load()
994 regs->gpr[ra] += regs->gpr[rb]; in mcheck_handle_load()
1003 regs->gpr[rd] = 0xffffffff; in mcheck_handle_load()
1007 regs->gpr[rd] = 0xffffffff; in mcheck_handle_load()
1008 regs->gpr[ra] += (s16)d; in mcheck_handle_load()
1012 regs->gpr[rd] = 0xff; in mcheck_handle_load()
1016 regs->gpr[rd] = 0xff; in mcheck_handle_load()
1017 regs->gpr[ra] += (s16)d; in mcheck_handle_load()
1021 regs->gpr[rd] = 0xffff; in mcheck_handle_load()
1025 regs->gpr[rd] = 0xffff; in mcheck_handle_load()
1026 regs->gpr[ra] += (s16)d; in mcheck_handle_load()
1030 regs->gpr[rd] = ~0UL; in mcheck_handle_load()
1034 regs->gpr[rd] = ~0UL; in mcheck_handle_load()
1035 regs->gpr[ra] += (s16)d; in mcheck_handle_load()
1052 if (!(hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG)) in is_in_pci_mem_space()
1056 res = &hose->mem_resources[i]; in is_in_pci_mem_space()
1057 if ((res->flags & IORESOURCE_MEM) && in is_in_pci_mem_space()
1058 addr >= res->start && addr <= res->end) in is_in_pci_mem_space()
1072 if (regs->msr & MSR_GS) in fsl_pci_mcheck_exception()
1084 (void __user *)regs->nip, sizeof(inst)); in fsl_pci_mcheck_exception()
1086 ret = get_kernel_nofault(inst, (void *)regs->nip); in fsl_pci_mcheck_exception()
1100 { .compatible = "fsl,mpc8540-pci", },
1101 { .compatible = "fsl,mpc8548-pcie", },
1102 { .compatible = "fsl,mpc8610-pci", },
1103 { .compatible = "fsl,mpc8641-pcie", },
1104 { .compatible = "fsl,qoriq-pcie", },
1105 { .compatible = "fsl,qoriq-pcie-v2.1", },
1106 { .compatible = "fsl,qoriq-pcie-v2.2", },
1107 { .compatible = "fsl,qoriq-pcie-v2.3", },
1108 { .compatible = "fsl,qoriq-pcie-v2.4", },
1109 { .compatible = "fsl,qoriq-pcie-v3.0", },
1115 { .compatible = "fsl,p1022-pcie", },
1116 { .compatible = "fsl,p4080-pcie", },
1157 * various bugs with primary-less systems are fixed. in fsl_pci_assign_primary()
1171 struct ccsr_pci __iomem *pci = hose->private_data; in fsl_pci_pme_handle()
1174 dr = in_be32(&pci->pex_pme_mes_dr); in fsl_pci_pme_handle()
1178 out_be32(&pci->pex_pme_mes_dr, dr); in fsl_pci_pme_handle()
1192 dev = list_first_entry(&hose->bus->devices, typeof(*dev), bus_list); in fsl_pci_pme_probe()
1195 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pms); in fsl_pci_pme_probe()
1197 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pms); in fsl_pci_pme_probe()
1199 pme_irq = irq_of_parse_and_map(hose->dn, 0); in fsl_pci_pme_probe()
1201 dev_err(&dev->dev, "Failed to map PME interrupt.\n"); in fsl_pci_pme_probe()
1203 return -ENXIO; in fsl_pci_pme_probe()
1206 res = devm_request_irq(hose->parent, pme_irq, in fsl_pci_pme_probe()
1211 dev_err(&dev->dev, "Unable to request irq %d for PME\n", pme_irq); in fsl_pci_pme_probe()
1214 return -ENODEV; in fsl_pci_pme_probe()
1217 pci = hose->private_data; in fsl_pci_pme_probe()
1220 clrbits32(&pci->pex_pme_mes_disr, in fsl_pci_pme_probe()
1223 out_be32(&pci->pex_pme_mes_ier, 0); in fsl_pci_pme_probe()
1224 setbits32(&pci->pex_pme_mes_ier, in fsl_pci_pme_probe()
1228 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pms); in fsl_pci_pme_probe()
1230 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pms); in fsl_pci_pme_probe()
1237 struct ccsr_pci __iomem *pci = hose->private_data; in send_pme_turnoff_message()
1242 setbits32(&pci->pex_pmcr, PEX_PMCR_PTOMR); in send_pme_turnoff_message()
1246 dr = in_be32(&pci->pex_pme_mes_dr); in send_pme_turnoff_message()
1248 out_be32(&pci->pex_pme_mes_dr, dr); in send_pme_turnoff_message()
1273 struct ccsr_pci __iomem *pci = hose->private_data; in fsl_pci_syscore_do_resume()
1278 setbits32(&pci->pex_pmcr, PEX_PMCR_EXL2S); in fsl_pci_syscore_do_resume()
1282 dr = in_be32(&pci->pex_pme_mes_dr); in fsl_pci_syscore_do_resume()
1284 out_be32(&pci->pex_pme_mes_dr, dr); in fsl_pci_syscore_do_resume()
1319 .of_node = pdev->dev.of_node in add_err_dev()
1322 errdev = platform_device_register_resndata(&pdev->dev, in add_err_dev()
1323 "mpc85xx-pci-edac", in add_err_dev()
1325 pdev->resource, in add_err_dev()
1326 pdev->num_resources, in add_err_dev()
1337 node = pdev->dev.of_node; in fsl_pci_probe()
1344 dev_err(&pdev->dev, "couldn't register error device: %d\n", in fsl_pci_probe()
1352 .name = "fsl-pci",