1 // SPDX-License-Identifier: GPL-2.0-only
7  * Copyright 2007-2008,2010 Freescale Semiconductor, Inc.
11  * Copyright (c) 1999-2001 Dan Malek <dan@embeddedalley.com>
39 		return -ENODEV;  in cpm_init()
68 			  (CONFIG_PPC_EARLY_DEBUG_CPM_ADDR - PHYS_IMMR_BASE +  in udbg_init_cpm()
71 			 (in_be32(&cpm_udbg_txdesc[1]) - PHYS_IMMR_BASE +  in udbg_init_cpm()
81 		setbat(1, 0xf0000000, 0xf0000000, 1024*1024, PAGE_KERNEL_NCG);  in udbg_init_cpm()
108 	struct cpm2_ioports __iomem *iop = cpm2_gc->regs;  in cpm2_gpio32_save_regs()
110 	cpm2_gc->cpdata = in_be32(&iop->dat);  in cpm2_gpio32_save_regs()
116 	struct cpm2_ioports __iomem *iop = cpm2_gc->regs;  in cpm2_gpio32_get()
119 	pin_mask = 1 << (31 - gpio);  in cpm2_gpio32_get()
121 	return !!(in_be32(&iop->dat) & pin_mask);  in cpm2_gpio32_get()
126 	struct cpm2_ioports __iomem *iop = cpm2_gc->regs;  in __cpm2_gpio32_set()
129 		cpm2_gc->cpdata |= pin_mask;  in __cpm2_gpio32_set()
131 		cpm2_gc->cpdata &= ~pin_mask;  in __cpm2_gpio32_set()
133 	out_be32(&iop->dat, cpm2_gc->cpdata);  in __cpm2_gpio32_set()
140 	u32 pin_mask = 1 << (31 - gpio);  in cpm2_gpio32_set()
142 	spin_lock_irqsave(&cpm2_gc->lock, flags);  in cpm2_gpio32_set()
146 	spin_unlock_irqrestore(&cpm2_gc->lock, flags);  in cpm2_gpio32_set()
154 	struct cpm2_ioports __iomem *iop = cpm2_gc->regs;  in cpm2_gpio32_dir_out()
156 	u32 pin_mask = 1 << (31 - gpio);  in cpm2_gpio32_dir_out()
158 	spin_lock_irqsave(&cpm2_gc->lock, flags);  in cpm2_gpio32_dir_out()
160 	setbits32(&iop->dir, pin_mask);  in cpm2_gpio32_dir_out()
163 	spin_unlock_irqrestore(&cpm2_gc->lock, flags);  in cpm2_gpio32_dir_out()
171 	struct cpm2_ioports __iomem *iop = cpm2_gc->regs;  in cpm2_gpio32_dir_in()
173 	u32 pin_mask = 1 << (31 - gpio);  in cpm2_gpio32_dir_in()
175 	spin_lock_irqsave(&cpm2_gc->lock, flags);  in cpm2_gpio32_dir_in()
177 	clrbits32(&iop->dir, pin_mask);  in cpm2_gpio32_dir_in()
179 	spin_unlock_irqrestore(&cpm2_gc->lock, flags);  in cpm2_gpio32_dir_in()
186 	struct device_node *np = dev->of_node;  in cpm2_gpiochip_add32()
192 		return -ENOMEM;  in cpm2_gpiochip_add32()
194 	spin_lock_init(&cpm2_gc->lock);  in cpm2_gpiochip_add32()
196 	gc = &cpm2_gc->gc;  in cpm2_gpiochip_add32()
198 	gc->base = -1;  in cpm2_gpiochip_add32()
199 	gc->ngpio = 32;  in cpm2_gpiochip_add32()
200 	gc->direction_input = cpm2_gpio32_dir_in;  in cpm2_gpiochip_add32()
201 	gc->direction_output = cpm2_gpio32_dir_out;  in cpm2_gpiochip_add32()
202 	gc->get = cpm2_gpio32_get;  in cpm2_gpiochip_add32()
203 	gc->set = cpm2_gpio32_set;  in cpm2_gpiochip_add32()
204 	gc->parent = dev;  in cpm2_gpiochip_add32()
205 	gc->owner = THIS_MODULE;  in cpm2_gpiochip_add32()
207 	gc->label = devm_kasprintf(dev, GFP_KERNEL, "%pOF", np);  in cpm2_gpiochip_add32()
208 	if (!gc->label)  in cpm2_gpiochip_add32()
209 		return -ENOMEM;  in cpm2_gpiochip_add32()
211 	cpm2_gc->regs = devm_of_iomap(dev, np, 0, NULL);  in cpm2_gpiochip_add32()
212 	if (IS_ERR(cpm2_gc->regs))  in cpm2_gpiochip_add32()
213 		return PTR_ERR(cpm2_gc->regs);  in cpm2_gpiochip_add32()