Lines Matching full:pe
49 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
52 void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, in pe_level_printk() argument
64 if (pe->flags & PNV_IODA_PE_DEV) in pe_level_printk()
65 strscpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); in pe_level_printk()
66 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) in pe_level_printk()
68 pci_domain_nr(pe->pbus), pe->pbus->number); in pe_level_printk()
70 else if (pe->flags & PNV_IODA_PE_VF) in pe_level_printk()
72 pci_domain_nr(pe->parent_dev->bus), in pe_level_printk()
73 (pe->rid & 0xff00) >> 8, in pe_level_printk()
74 PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); in pe_level_printk()
77 printk("%spci %s: [PE# %.2x] %pV", in pe_level_printk()
78 level, pfix, pe->pe_number, &vaf); in pe_level_printk()
123 * Clear the PE frozen state as it might be put into frozen state in pnv_ioda_init_pe()
125 * PE is already in unfrozen state. in pnv_ioda_init_pe()
130 pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n", in pnv_ioda_init_pe()
139 pr_warn("%s: Invalid PE %x on PHB#%x\n", in pnv_ioda_reserve_pe()
146 pr_debug("%s: PE %x was reserved on PHB#%x\n", in pnv_ioda_reserve_pe()
156 int run = 0, pe, i; in pnv_ioda_alloc_pe() local
161 for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) { in pnv_ioda_alloc_pe()
162 if (test_bit(pe, phb->ioda.pe_alloc)) { in pnv_ioda_alloc_pe()
174 for (i = pe; i < pe + count; i++) { in pnv_ioda_alloc_pe()
178 ret = &phb->ioda.pe_array[pe]; in pnv_ioda_alloc_pe()
185 void pnv_ioda_free_pe(struct pnv_ioda_pe *pe) in pnv_ioda_free_pe() argument
187 struct pnv_phb *phb = pe->phb; in pnv_ioda_free_pe()
188 unsigned int pe_num = pe->pe_number; in pnv_ioda_free_pe()
190 WARN_ON(pe->pdev); in pnv_ioda_free_pe()
191 memset(pe, 0, sizeof(struct pnv_ioda_pe)); in pnv_ioda_free_pe()
228 * Exclude the segments for reserved and root bus PE, which in pnv_ioda2_init_m64()
237 pr_warn(" Cannot strip M64 segment for reserved PE#%x\n", in pnv_ioda2_init_m64()
296 struct pnv_ioda_pe *master_pe, *pe; in pnv_ioda_pick_m64_pe() local
313 /* Figure out reserved PE numbers by the PE */ in pnv_ioda_pick_m64_pe()
319 * pick M64 dependent PE#. in pnv_ioda_pick_m64_pe()
327 * Figure out the master PE and put all slave PEs to master in pnv_ioda_pick_m64_pe()
328 * PE's list to form compound PE. in pnv_ioda_pick_m64_pe()
334 pe = &phb->ioda.pe_array[i]; in pnv_ioda_pick_m64_pe()
336 phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number; in pnv_ioda_pick_m64_pe()
338 pe->flags |= PNV_IODA_PE_MASTER; in pnv_ioda_pick_m64_pe()
339 INIT_LIST_HEAD(&pe->slaves); in pnv_ioda_pick_m64_pe()
340 master_pe = pe; in pnv_ioda_pick_m64_pe()
342 pe->flags |= PNV_IODA_PE_SLAVE; in pnv_ioda_pick_m64_pe()
343 pe->master = master_pe; in pnv_ioda_pick_m64_pe()
344 list_add_tail(&pe->list, &master_pe->slaves); in pnv_ioda_pick_m64_pe()
441 struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; in pnv_ioda_freeze_pe() local
445 /* Fetch master PE */ in pnv_ioda_freeze_pe()
446 if (pe->flags & PNV_IODA_PE_SLAVE) { in pnv_ioda_freeze_pe()
447 pe = pe->master; in pnv_ioda_freeze_pe()
448 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) in pnv_ioda_freeze_pe()
451 pe_no = pe->pe_number; in pnv_ioda_freeze_pe()
454 /* Freeze master PE */ in pnv_ioda_freeze_pe()
459 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", in pnv_ioda_freeze_pe()
465 if (!(pe->flags & PNV_IODA_PE_MASTER)) in pnv_ioda_freeze_pe()
468 list_for_each_entry(slave, &pe->slaves, list) { in pnv_ioda_freeze_pe()
473 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", in pnv_ioda_freeze_pe()
481 struct pnv_ioda_pe *pe, *slave; in pnv_ioda_unfreeze_pe() local
484 /* Find master PE */ in pnv_ioda_unfreeze_pe()
485 pe = &phb->ioda.pe_array[pe_no]; in pnv_ioda_unfreeze_pe()
486 if (pe->flags & PNV_IODA_PE_SLAVE) { in pnv_ioda_unfreeze_pe()
487 pe = pe->master; in pnv_ioda_unfreeze_pe()
488 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); in pnv_ioda_unfreeze_pe()
489 pe_no = pe->pe_number; in pnv_ioda_unfreeze_pe()
492 /* Clear frozen state for master PE */ in pnv_ioda_unfreeze_pe()
495 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", in pnv_ioda_unfreeze_pe()
500 if (!(pe->flags & PNV_IODA_PE_MASTER)) in pnv_ioda_unfreeze_pe()
504 list_for_each_entry(slave, &pe->slaves, list) { in pnv_ioda_unfreeze_pe()
509 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", in pnv_ioda_unfreeze_pe()
521 struct pnv_ioda_pe *slave, *pe; in pnv_ioda_get_pe_state() local
526 /* Sanity check on PE number */ in pnv_ioda_get_pe_state()
531 * Fetch the master PE and the PE instance might be in pnv_ioda_get_pe_state()
534 pe = &phb->ioda.pe_array[pe_no]; in pnv_ioda_get_pe_state()
535 if (pe->flags & PNV_IODA_PE_SLAVE) { in pnv_ioda_get_pe_state()
536 pe = pe->master; in pnv_ioda_get_pe_state()
537 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); in pnv_ioda_get_pe_state()
538 pe_no = pe->pe_number; in pnv_ioda_get_pe_state()
541 /* Check the master PE */ in pnv_ioda_get_pe_state()
546 "PHB#%x-PE#%x state\n", in pnv_ioda_get_pe_state()
552 /* Check the slave PE */ in pnv_ioda_get_pe_state()
553 if (!(pe->flags & PNV_IODA_PE_MASTER)) in pnv_ioda_get_pe_state()
556 list_for_each_entry(slave, &pe->slaves, list) { in pnv_ioda_get_pe_state()
564 "PHB#%x-PE#%x state\n", in pnv_ioda_get_pe_state()
614 /* Parent PE affects child PE */ in pnv_ioda_set_one_peltv()
626 /* Compound case: parent PE affects slave PEs */ in pnv_ioda_set_one_peltv()
641 struct pnv_ioda_pe *pe, in pnv_ioda_set_peltv() argument
649 * Clear PE frozen state. If it's master PE, we need in pnv_ioda_set_peltv()
650 * clear slave PE frozen state as well. in pnv_ioda_set_peltv()
653 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, in pnv_ioda_set_peltv()
655 if (pe->flags & PNV_IODA_PE_MASTER) { in pnv_ioda_set_peltv()
656 list_for_each_entry(slave, &pe->slaves, list) in pnv_ioda_set_peltv()
664 * Associate PE in PELT. We need add the PE into the in pnv_ioda_set_peltv()
666 * originated from the PE might contribute to other in pnv_ioda_set_peltv()
669 ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); in pnv_ioda_set_peltv()
674 if (pe->flags & PNV_IODA_PE_MASTER) { in pnv_ioda_set_peltv()
675 list_for_each_entry(slave, &pe->slaves, list) { in pnv_ioda_set_peltv()
676 ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); in pnv_ioda_set_peltv()
682 if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) in pnv_ioda_set_peltv()
683 pdev = pe->pbus->self; in pnv_ioda_set_peltv()
684 else if (pe->flags & PNV_IODA_PE_DEV) in pnv_ioda_set_peltv()
685 pdev = pe->pdev->bus->self; in pnv_ioda_set_peltv()
687 else if (pe->flags & PNV_IODA_PE_VF) in pnv_ioda_set_peltv()
688 pdev = pe->parent_dev; in pnv_ioda_set_peltv()
696 ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); in pnv_ioda_set_peltv()
708 struct pnv_ioda_pe *pe, in pnv_ioda_unset_peltv() argument
718 pe->pe_number, in pnv_ioda_unset_peltv()
725 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, in pnv_ioda_unset_peltv()
728 /* Disassociate PE in PELT */ in pnv_ioda_unset_peltv()
729 rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, in pnv_ioda_unset_peltv()
730 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); in pnv_ioda_unset_peltv()
732 pe_warn(pe, "OPAL error %lld remove self from PELTV\n", rc); in pnv_ioda_unset_peltv()
735 int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) in pnv_ioda_deconfigure_pe() argument
742 /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ in pnv_ioda_deconfigure_pe()
743 if (pe->pbus) { in pnv_ioda_deconfigure_pe()
748 parent = pe->pbus->self; in pnv_ioda_deconfigure_pe()
749 if (pe->flags & PNV_IODA_PE_BUS_ALL) in pnv_ioda_deconfigure_pe()
750 count = resource_size(&pe->pbus->busn_res); in pnv_ioda_deconfigure_pe()
762 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", in pnv_ioda_deconfigure_pe()
767 rid_end = pe->rid + (count << 8); in pnv_ioda_deconfigure_pe()
770 if (pe->flags & PNV_IODA_PE_VF) in pnv_ioda_deconfigure_pe()
771 parent = pe->parent_dev; in pnv_ioda_deconfigure_pe()
774 parent = pe->pdev->bus->self; in pnv_ioda_deconfigure_pe()
778 rid_end = pe->rid + 1; in pnv_ioda_deconfigure_pe()
782 for (rid = pe->rid; rid < rid_end; rid++) in pnv_ioda_deconfigure_pe()
790 pnv_ioda_unset_peltv(phb, pe, parent); in pnv_ioda_deconfigure_pe()
792 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, in pnv_ioda_deconfigure_pe()
795 pe_err(pe, "OPAL error %lld trying to setup PELT table\n", rc); in pnv_ioda_deconfigure_pe()
797 pe->pbus = NULL; in pnv_ioda_deconfigure_pe()
798 pe->pdev = NULL; in pnv_ioda_deconfigure_pe()
800 pe->parent_dev = NULL; in pnv_ioda_deconfigure_pe()
806 int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) in pnv_ioda_configure_pe() argument
812 if (pe->pbus) { in pnv_ioda_configure_pe()
817 if (pe->flags & PNV_IODA_PE_BUS_ALL) in pnv_ioda_configure_pe()
818 count = resource_size(&pe->pbus->busn_res); in pnv_ioda_configure_pe()
830 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", in pnv_ioda_configure_pe()
835 rid_end = pe->rid + (count << 8); in pnv_ioda_configure_pe()
840 rid_end = pe->rid + 1; in pnv_ioda_configure_pe()
844 * Associate PE in PELT. We need add the PE into the in pnv_ioda_configure_pe()
846 * originated from the PE might contribute to other in pnv_ioda_configure_pe()
849 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, in pnv_ioda_configure_pe()
852 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); in pnv_ioda_configure_pe()
861 pnv_ioda_set_peltv(phb, pe, true); in pnv_ioda_configure_pe()
864 for (rid = pe->rid; rid < rid_end; rid++) in pnv_ioda_configure_pe()
865 phb->ioda.pe_rmap[rid] = pe->pe_number; in pnv_ioda_configure_pe()
867 pe->mve_number = 0; in pnv_ioda_configure_pe()
876 struct pnv_ioda_pe *pe; in pnv_ioda_setup_dev_PE() local
886 pe = pnv_ioda_alloc_pe(phb, 1); in pnv_ioda_setup_dev_PE()
887 if (!pe) { in pnv_ioda_setup_dev_PE()
888 pr_warn("%s: Not enough PE# available, disabling device\n", in pnv_ioda_setup_dev_PE()
893 /* NOTE: We don't get a reference for the pointer in the PE in pnv_ioda_setup_dev_PE()
894 * data structure, both the device and PE structures should be in pnv_ioda_setup_dev_PE()
899 pdn->pe_number = pe->pe_number; in pnv_ioda_setup_dev_PE()
900 pe->flags = PNV_IODA_PE_DEV; in pnv_ioda_setup_dev_PE()
901 pe->pdev = dev; in pnv_ioda_setup_dev_PE()
902 pe->pbus = NULL; in pnv_ioda_setup_dev_PE()
903 pe->mve_number = -1; in pnv_ioda_setup_dev_PE()
904 pe->rid = dev->bus->number << 8 | pdn->devfn; in pnv_ioda_setup_dev_PE()
905 pe->device_count++; in pnv_ioda_setup_dev_PE()
907 pe_info(pe, "Associated device to PE\n"); in pnv_ioda_setup_dev_PE()
909 if (pnv_ioda_configure_pe(phb, pe)) { in pnv_ioda_setup_dev_PE()
911 pnv_ioda_free_pe(pe); in pnv_ioda_setup_dev_PE()
913 pe->pdev = NULL; in pnv_ioda_setup_dev_PE()
917 /* Put PE to the list */ in pnv_ioda_setup_dev_PE()
919 list_add_tail(&pe->list, &phb->ioda.pe_list); in pnv_ioda_setup_dev_PE()
921 return pe; in pnv_ioda_setup_dev_PE()
927 * subordinate PCI devices and buses. The second type of PE is normally
933 struct pnv_ioda_pe *pe = NULL; in pnv_ioda_setup_bus_PE() local
937 * In partial hotplug case, the PE instance might be still alive. in pnv_ioda_setup_bus_PE()
942 pe = &phb->ioda.pe_array[pe_num]; in pnv_ioda_setup_bus_PE()
946 /* PE number for root bus should have been reserved */ in pnv_ioda_setup_bus_PE()
948 pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx]; in pnv_ioda_setup_bus_PE()
950 /* Check if PE is determined by M64 */ in pnv_ioda_setup_bus_PE()
951 if (!pe) in pnv_ioda_setup_bus_PE()
952 pe = pnv_ioda_pick_m64_pe(bus, all); in pnv_ioda_setup_bus_PE()
954 /* The PE number isn't pinned by M64 */ in pnv_ioda_setup_bus_PE()
955 if (!pe) in pnv_ioda_setup_bus_PE()
956 pe = pnv_ioda_alloc_pe(phb, 1); in pnv_ioda_setup_bus_PE()
958 if (!pe) { in pnv_ioda_setup_bus_PE()
959 pr_warn("%s: Not enough PE# available for PCI bus %04x:%02x\n", in pnv_ioda_setup_bus_PE()
964 pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); in pnv_ioda_setup_bus_PE()
965 pe->pbus = bus; in pnv_ioda_setup_bus_PE()
966 pe->pdev = NULL; in pnv_ioda_setup_bus_PE()
967 pe->mve_number = -1; in pnv_ioda_setup_bus_PE()
968 pe->rid = bus->busn_res.start << 8; in pnv_ioda_setup_bus_PE()
971 pe_info(pe, "Secondary bus %pad..%pad associated with PE#%x\n", in pnv_ioda_setup_bus_PE()
973 pe->pe_number); in pnv_ioda_setup_bus_PE()
975 pe_info(pe, "Secondary bus %pad associated with PE#%x\n", in pnv_ioda_setup_bus_PE()
976 &bus->busn_res.start, pe->pe_number); in pnv_ioda_setup_bus_PE()
978 if (pnv_ioda_configure_pe(phb, pe)) { in pnv_ioda_setup_bus_PE()
980 pnv_ioda_free_pe(pe); in pnv_ioda_setup_bus_PE()
981 pe->pbus = NULL; in pnv_ioda_setup_bus_PE()
985 /* Put PE to the list */ in pnv_ioda_setup_bus_PE()
986 list_add_tail(&pe->list, &phb->ioda.pe_list); in pnv_ioda_setup_bus_PE()
988 return pe; in pnv_ioda_setup_bus_PE()
995 struct pnv_ioda_pe *pe; in pnv_pci_ioda_dma_dev_setup() local
997 /* Check if the BDFN for this device is associated with a PE yet */ in pnv_pci_ioda_dma_dev_setup()
998 pe = pnv_pci_bdfn_to_pe(phb, pci_dev_id(pdev)); in pnv_pci_ioda_dma_dev_setup()
999 if (!pe) { in pnv_pci_ioda_dma_dev_setup()
1005 pe = pnv_pci_bdfn_to_pe(phb, pci_dev_id(pdev)); in pnv_pci_ioda_dma_dev_setup()
1006 pci_info(pdev, "Configured PE#%x\n", pe ? pe->pe_number : 0xfffff); in pnv_pci_ioda_dma_dev_setup()
1010 * If we can't setup the IODA PE something has gone horribly in pnv_pci_ioda_dma_dev_setup()
1013 if (WARN_ON(!pe)) in pnv_pci_ioda_dma_dev_setup()
1016 pci_info(pdev, "Added to existing PE#%x\n", pe->pe_number); in pnv_pci_ioda_dma_dev_setup()
1023 if (!pe->dma_setup_done && !pci_is_bridge(pdev)) { in pnv_pci_ioda_dma_dev_setup()
1026 pnv_pci_ioda2_setup_dma_pe(phb, pe); in pnv_pci_ioda_dma_dev_setup()
1035 pdn->pe_number = pe->pe_number; in pnv_pci_ioda_dma_dev_setup()
1036 pe->device_count++; in pnv_pci_ioda_dma_dev_setup()
1039 pdev->dev.archdata.dma_offset = pe->tce_bypass_base; in pnv_pci_ioda_dma_dev_setup()
1040 set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); in pnv_pci_ioda_dma_dev_setup()
1043 if (pe->table_group.group) in pnv_pci_ioda_dma_dev_setup()
1044 iommu_add_device(&pe->table_group, &pdev->dev); in pnv_pci_ioda_dma_dev_setup()
1050 * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses.
1064 static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe) in pnv_pci_ioda_dma_64bit_bypass() argument
1083 table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL, in pnv_pci_ioda_dma_64bit_bypass()
1099 rc = opal_pci_map_pe_dma_window(pe->phb->opal_id, in pnv_pci_ioda_dma_64bit_bypass()
1100 pe->pe_number, in pnv_pci_ioda_dma_64bit_bypass()
1102 (pe->pe_number << 1) + 0, in pnv_pci_ioda_dma_64bit_bypass()
1108 pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n"); in pnv_pci_ioda_dma_64bit_bypass()
1112 pe_err(pe, "Error configuring 64-bit DMA bypass\n"); in pnv_pci_ioda_dma_64bit_bypass()
1121 struct pnv_ioda_pe *pe; in pnv_pci_ioda_iommu_bypass_supported() local
1126 pe = &phb->ioda.pe_array[pdn->pe_number]; in pnv_pci_ioda_iommu_bypass_supported()
1127 if (pe->tce_bypass_enabled) { in pnv_pci_ioda_iommu_bypass_supported()
1128 u64 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; in pnv_pci_ioda_iommu_bypass_supported()
1141 /* pe->pdev should be set if it's a single device, pe->pbus if not */ in pnv_pci_ioda_iommu_bypass_supported()
1142 (pe->device_count == 1 || !pe->pbus) && in pnv_pci_ioda_iommu_bypass_supported()
1145 s64 rc = pnv_pci_ioda_dma_64bit_bypass(pe); in pnv_pci_ioda_iommu_bypass_supported()
1174 static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe) in pnv_pci_phb3_tce_invalidate_pe() argument
1176 /* 01xb - invalidate TCEs that match the specified PE# */ in pnv_pci_phb3_tce_invalidate_pe()
1177 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb); in pnv_pci_phb3_tce_invalidate_pe()
1178 unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF); in pnv_pci_phb3_tce_invalidate_pe()
1184 static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, in pnv_pci_phb3_tce_invalidate() argument
1188 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb); in pnv_pci_phb3_tce_invalidate()
1191 /* We'll invalidate DMA address in PE scope */ in pnv_pci_phb3_tce_invalidate()
1193 start |= (pe->pe_number & 0xFF); in pnv_pci_phb3_tce_invalidate()
1208 static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe) in pnv_pci_ioda2_tce_invalidate_pe() argument
1210 struct pnv_phb *phb = pe->phb; in pnv_pci_ioda2_tce_invalidate_pe()
1213 pnv_pci_phb3_tce_invalidate_pe(pe); in pnv_pci_ioda2_tce_invalidate_pe()
1216 pe->pe_number, 0, 0, 0); in pnv_pci_ioda2_tce_invalidate_pe()
1225 struct pnv_ioda_pe *pe = container_of(tgl->table_group, in pnv_pci_ioda2_tce_invalidate() local
1227 struct pnv_phb *phb = pe->phb; in pnv_pci_ioda2_tce_invalidate()
1231 pnv_pci_phb3_tce_invalidate(pe, shift, in pnv_pci_ioda2_tce_invalidate()
1236 pe->pe_number, 1u << shift, in pnv_pci_ioda2_tce_invalidate()
1278 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, in pnv_pci_ioda2_set_window() local
1280 struct pnv_phb *phb = pe->phb; in pnv_pci_ioda2_set_window()
1287 pe_info(pe, "Setting up window#%d %llx..%llx pg=%lx\n", in pnv_pci_ioda2_set_window()
1292 * Map TCE table through TVT. The TVE index is the PE number in pnv_pci_ioda2_set_window()
1296 pe->pe_number, in pnv_pci_ioda2_set_window()
1297 (pe->pe_number << 1) + num, in pnv_pci_ioda2_set_window()
1303 pe_err(pe, "Failed to configure TCE table, err %lld\n", rc); in pnv_pci_ioda2_set_window()
1308 tbl, &pe->table_group); in pnv_pci_ioda2_set_window()
1309 pnv_pci_ioda2_tce_invalidate_pe(pe); in pnv_pci_ioda2_set_window()
1314 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) in pnv_pci_ioda2_set_bypass() argument
1316 uint16_t window_id = (pe->pe_number << 1 ) + 1; in pnv_pci_ioda2_set_bypass()
1319 pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); in pnv_pci_ioda2_set_bypass()
1324 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, in pnv_pci_ioda2_set_bypass()
1325 pe->pe_number, in pnv_pci_ioda2_set_bypass()
1327 pe->tce_bypass_base, in pnv_pci_ioda2_set_bypass()
1330 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, in pnv_pci_ioda2_set_bypass()
1331 pe->pe_number, in pnv_pci_ioda2_set_bypass()
1333 pe->tce_bypass_base, in pnv_pci_ioda2_set_bypass()
1337 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); in pnv_pci_ioda2_set_bypass()
1339 pe->tce_bypass_enabled = enable; in pnv_pci_ioda2_set_bypass()
1346 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, in pnv_pci_ioda2_create_table() local
1348 int nid = pe->phb->hose->node; in pnv_pci_ioda2_create_table()
1349 __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; in pnv_pci_ioda2_create_table()
1372 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) in pnv_pci_ioda2_setup_default_config() argument
1414 rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, PAGE_SHIFT, in pnv_pci_ioda2_setup_default_config()
1417 pe_err(pe, "Failed to create 32-bit TCE table, err %ld", in pnv_pci_ioda2_setup_default_config()
1425 if (window_size > pe->phb->ioda.m32_pci_base) { in pnv_pci_ioda2_setup_default_config()
1426 res_start = pe->phb->ioda.m32_pci_base >> tbl->it_page_shift; in pnv_pci_ioda2_setup_default_config()
1430 tbl->it_index = (pe->phb->hose->global_number << 16) | pe->pe_number; in pnv_pci_ioda2_setup_default_config()
1431 if (iommu_init_table(tbl, pe->phb->hose->node, res_start, res_end)) in pnv_pci_ioda2_setup_default_config()
1432 rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); in pnv_pci_ioda2_setup_default_config()
1436 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", rc); in pnv_pci_ioda2_setup_default_config()
1441 pnv_pci_ioda2_set_bypass(pe, true); in pnv_pci_ioda2_setup_default_config()
1448 if (pe->pdev) in pnv_pci_ioda2_setup_default_config()
1449 set_iommu_table_base(&pe->pdev->dev, tbl); in pnv_pci_ioda2_setup_default_config()
1457 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, in pnv_pci_ioda2_unset_window() local
1459 struct pnv_phb *phb = pe->phb; in pnv_pci_ioda2_unset_window()
1462 pe_info(pe, "Removing DMA window #%d\n", num); in pnv_pci_ioda2_unset_window()
1464 ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, in pnv_pci_ioda2_unset_window()
1465 (pe->pe_number << 1) + num, in pnv_pci_ioda2_unset_window()
1469 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); in pnv_pci_ioda2_unset_window()
1471 pnv_pci_ioda2_tce_invalidate_pe(pe); in pnv_pci_ioda2_unset_window()
1525 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus) in pnv_ioda_setup_bus_dma() argument
1530 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); in pnv_ioda_setup_bus_dma()
1531 dev->dev.archdata.dma_offset = pe->tce_bypass_base; in pnv_ioda_setup_bus_dma()
1533 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) in pnv_ioda_setup_bus_dma()
1534 pnv_ioda_setup_bus_dma(pe, dev->subordinate); in pnv_ioda_setup_bus_dma()
1541 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, in pnv_ioda2_take_ownership() local
1544 struct iommu_table *tbl = pe->table_group.tables[0]; in pnv_ioda2_take_ownership()
1553 pnv_pci_ioda2_set_bypass(pe, false); in pnv_ioda2_take_ownership()
1554 pnv_pci_ioda2_unset_window(&pe->table_group, 0); in pnv_ioda2_take_ownership()
1555 if (pe->pbus) in pnv_ioda2_take_ownership()
1556 pnv_ioda_setup_bus_dma(pe, pe->pbus); in pnv_ioda2_take_ownership()
1557 else if (pe->pdev) in pnv_ioda2_take_ownership()
1558 set_iommu_table_base(&pe->pdev->dev, NULL); in pnv_ioda2_take_ownership()
1567 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, in pnv_ioda2_release_ownership() local
1571 if (pe->table_group.tables[0]) in pnv_ioda2_release_ownership()
1573 pnv_pci_ioda2_setup_default_config(pe); in pnv_ioda2_release_ownership()
1574 if (pe->pbus) in pnv_ioda2_release_ownership()
1575 pnv_ioda_setup_bus_dma(pe, pe->pbus); in pnv_ioda2_release_ownership()
1589 struct pnv_ioda_pe *pe) in pnv_pci_ioda2_setup_dma_pe() argument
1594 pe->tce_bypass_base = 1ull << 59; in pnv_pci_ioda2_setup_dma_pe()
1596 /* The PE will reserve all possible 32-bits space */ in pnv_pci_ioda2_setup_dma_pe()
1597 pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", in pnv_pci_ioda2_setup_dma_pe()
1601 pe->table_group.tce32_start = 0; in pnv_pci_ioda2_setup_dma_pe()
1602 pe->table_group.tce32_size = phb->ioda.m32_pci_base; in pnv_pci_ioda2_setup_dma_pe()
1603 pe->table_group.max_dynamic_windows_supported = in pnv_pci_ioda2_setup_dma_pe()
1605 pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; in pnv_pci_ioda2_setup_dma_pe()
1606 pe->table_group.pgsizes = pnv_ioda_parse_tce_sizes(phb); in pnv_pci_ioda2_setup_dma_pe()
1608 rc = pnv_pci_ioda2_setup_default_config(pe); in pnv_pci_ioda2_setup_dma_pe()
1613 pe->table_group.ops = &pnv_pci_ioda2_ops; in pnv_pci_ioda2_setup_dma_pe()
1614 iommu_register_group(&pe->table_group, phb->hose->global_number, in pnv_pci_ioda2_setup_dma_pe()
1615 pe->pe_number); in pnv_pci_ioda2_setup_dma_pe()
1617 pe->dma_setup_done = true; in pnv_pci_ioda2_setup_dma_pe()
1653 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); in __pnv_pci_ioda_msi_setup() local
1660 /* No PE assigned ? bail out ... no MSI for you ! */ in __pnv_pci_ioda_msi_setup()
1661 if (pe == NULL) in __pnv_pci_ioda_msi_setup()
1665 if (pe->mve_number < 0) in __pnv_pci_ioda_msi_setup()
1672 /* Assign XIVE to PE */ in __pnv_pci_ioda_msi_setup()
1673 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); in __pnv_pci_ioda_msi_setup()
1675 pr_warn("%s: OPAL error %d setting XIVE %d PE\n", in __pnv_pci_ioda_msi_setup()
1683 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, in __pnv_pci_ioda_msi_setup()
1695 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, in __pnv_pci_ioda_msi_setup()
1914 static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, in pnv_ioda_setup_pe_res() argument
1917 struct pnv_phb *phb = pe->phb; in pnv_ioda_setup_pe_res()
1933 phb->ioda.io_segmap[index] = pe->pe_number; in pnv_ioda_setup_pe_res()
1935 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); in pnv_ioda_setup_pe_res()
1937 pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n", in pnv_ioda_setup_pe_res()
1938 __func__, rc, index, pe->pe_number); in pnv_ioda_setup_pe_res()
1957 phb->ioda.m32_segmap[index] = pe->pe_number; in pnv_ioda_setup_pe_res()
1959 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); in pnv_ioda_setup_pe_res()
1961 pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x", in pnv_ioda_setup_pe_res()
1962 __func__, rc, index, pe->pe_number); in pnv_ioda_setup_pe_res()
1973 * This function is supposed to be called on basis of PE from top
1975 * parent PE could be overridden by its child PEs if necessary.
1977 static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe) in pnv_ioda_setup_pe_seg() argument
1983 * NOTE: We only care PCI bus based PE for now. For PCI in pnv_ioda_setup_pe_seg()
1984 * device based PE, for example SRIOV sensitive VF should in pnv_ioda_setup_pe_seg()
1987 BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); in pnv_ioda_setup_pe_seg()
1989 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { in pnv_ioda_setup_pe_seg()
1991 pnv_ioda_setup_pe_res(pe, &pdev->resource[i]); in pnv_ioda_setup_pe_seg()
1994 * If the PE contains all subordinate PCI buses, the in pnv_ioda_setup_pe_seg()
1996 * the PE as well. in pnv_ioda_setup_pe_seg()
1998 if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev)) in pnv_ioda_setup_pe_seg()
2001 pnv_ioda_setup_pe_res(pe, in pnv_ioda_setup_pe_seg()
2032 struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_num]; in pnv_pci_ioda_pe_dump() local
2037 pe_warn(pe, "rid: %04x dev count: %2d flags: %s%s%s%s%s%s\n", in pnv_pci_ioda_pe_dump()
2038 pe->rid, pe->device_count, in pnv_pci_ioda_pe_dump()
2039 (pe->flags & PNV_IODA_PE_DEV) ? "dev " : "", in pnv_pci_ioda_pe_dump()
2040 (pe->flags & PNV_IODA_PE_BUS) ? "bus " : "", in pnv_pci_ioda_pe_dump()
2041 (pe->flags & PNV_IODA_PE_BUS_ALL) ? "all " : "", in pnv_pci_ioda_pe_dump()
2042 (pe->flags & PNV_IODA_PE_MASTER) ? "master " : "", in pnv_pci_ioda_pe_dump()
2043 (pe->flags & PNV_IODA_PE_SLAVE) ? "slave " : "", in pnv_pci_ioda_pe_dump()
2044 (pe->flags & PNV_IODA_PE_VF) ? "vf " : ""); in pnv_pci_ioda_pe_dump()
2125 * For now, we return I/O or M32 segment size for PE sensitive
2129 * The current PCI bus might be put into one PE, which was
2226 struct pnv_ioda_pe *pe; in pnv_pci_configure_bus() local
2229 dev_info(&bus->dev, "Configuring PE for bus\n"); in pnv_pci_configure_bus()
2231 /* Don't assign PE to PCI bus, which doesn't have subordinate devices */ in pnv_pci_configure_bus()
2239 * Assign PE. We might run here because of partial hotplug. in pnv_pci_configure_bus()
2240 * For the case, we just pick up the existing PE and should in pnv_pci_configure_bus()
2243 pe = pnv_ioda_setup_bus_PE(bus, all); in pnv_pci_configure_bus()
2244 if (!pe) in pnv_pci_configure_bus()
2247 pnv_ioda_setup_pe_seg(pe); in pnv_pci_configure_bus()
2256 * assign a PE
2264 pci_err(dev, "pci_enable_device() blocked, no PE assigned.\n"); in pnv_pci_enable_device_hook()
2274 struct pnv_ioda_pe *pe; in pnv_ocapi_enable_device_hook() local
2281 pe = pnv_ioda_setup_dev_PE(dev); in pnv_ocapi_enable_device_hook()
2282 if (!pe) in pnv_ocapi_enable_device_hook()
2288 void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe) in pnv_pci_ioda2_release_pe_dma() argument
2290 struct iommu_table *tbl = pe->table_group.tables[0]; in pnv_pci_ioda2_release_pe_dma()
2293 if (!pe->dma_setup_done) in pnv_pci_ioda2_release_pe_dma()
2296 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); in pnv_pci_ioda2_release_pe_dma()
2298 pe_warn(pe, "OPAL error %lld release DMA window\n", rc); in pnv_pci_ioda2_release_pe_dma()
2300 pnv_pci_ioda2_set_bypass(pe, false); in pnv_pci_ioda2_release_pe_dma()
2301 if (pe->table_group.group) { in pnv_pci_ioda2_release_pe_dma()
2302 iommu_group_put(pe->table_group.group); in pnv_pci_ioda2_release_pe_dma()
2303 WARN_ON(pe->table_group.group); in pnv_pci_ioda2_release_pe_dma()
2309 static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe, in pnv_ioda_free_pe_seg() argument
2313 struct pnv_phb *phb = pe->phb; in pnv_ioda_free_pe_seg()
2318 if (map[idx] != pe->pe_number) in pnv_ioda_free_pe_seg()
2325 pe_warn(pe, "Error %lld unmapping (%d) segment#%d\n", in pnv_ioda_free_pe_seg()
2332 static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe) in pnv_ioda_release_pe_seg() argument
2334 struct pnv_phb *phb = pe->phb; in pnv_ioda_release_pe_seg()
2337 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, in pnv_ioda_release_pe_seg()
2342 static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe) in pnv_ioda_release_pe() argument
2344 struct pnv_phb *phb = pe->phb; in pnv_ioda_release_pe()
2347 pe_info(pe, "Releasing PE\n"); in pnv_ioda_release_pe()
2350 list_del(&pe->list); in pnv_ioda_release_pe()
2355 pnv_pci_ioda2_release_pe_dma(pe); in pnv_ioda_release_pe()
2363 pnv_ioda_release_pe_seg(pe); in pnv_ioda_release_pe()
2364 pnv_ioda_deconfigure_pe(pe->phb, pe); in pnv_ioda_release_pe()
2366 /* Release slave PEs in the compound PE */ in pnv_ioda_release_pe()
2367 if (pe->flags & PNV_IODA_PE_MASTER) { in pnv_ioda_release_pe()
2368 list_for_each_entry_safe(slave, tmp, &pe->slaves, list) { in pnv_ioda_release_pe()
2375 * The PE for root bus can be removed because of hotplug in EEH in pnv_ioda_release_pe()
2376 * recovery for fenced PHB error. We need to mark the PE dead so in pnv_ioda_release_pe()
2377 * that it can be populated again in PCI hot add path. The PE in pnv_ioda_release_pe()
2380 if (phb->ioda.root_pe_idx == pe->pe_number) in pnv_ioda_release_pe()
2383 pnv_ioda_free_pe(pe); in pnv_ioda_release_pe()
2390 struct pnv_ioda_pe *pe; in pnv_pci_release_device() local
2392 /* The VF PE state is torn down when sriov_disable() is called */ in pnv_pci_release_device()
2412 * set the PE number in @pdn to an invalid one. Otherwise, the PE's in pnv_pci_release_device()
2414 * be increased on adding devices. It leads to unbalanced PE's device in pnv_pci_release_device()
2417 pe = &phb->ioda.pe_array[pdn->pe_number]; in pnv_pci_release_device()
2420 WARN_ON(--pe->device_count < 0); in pnv_pci_release_device()
2421 if (pe->device_count == 0) in pnv_pci_release_device()
2422 pnv_ioda_release_pe(pe); in pnv_pci_release_device()
2436 struct pnv_ioda_pe *pe; in pnv_pci_ioda_dma_bus_setup() local
2438 list_for_each_entry(pe, &phb->ioda.pe_list, list) { in pnv_pci_ioda_dma_bus_setup()
2439 if (!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))) in pnv_pci_ioda_dma_bus_setup()
2442 if (!pe->pbus) in pnv_pci_ioda_dma_bus_setup()
2445 if (bus->number == ((pe->rid >> 8) & 0xFF)) { in pnv_pci_ioda_dma_bus_setup()
2446 pe->pbus = bus; in pnv_pci_ioda_dma_bus_setup()
2457 struct pnv_ioda_pe *pe; in pnv_pci_device_group() local
2462 pe = pnv_pci_bdfn_to_pe(phb, pci_dev_id(pdev)); in pnv_pci_device_group()
2463 if (!pe) in pnv_pci_device_group()
2466 if (!pe->table_group.group) in pnv_pci_device_group()
2469 return iommu_group_ref_get(pe->table_group.group); in pnv_pci_device_group()
2591 prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); in pnv_pci_init_ioda_phb()
2595 /* Invalidate RID to PE# mapping */ in pnv_pci_init_ioda_phb()
2635 * Choose PE number for root bus, which shouldn't have in pnv_pci_init_ioda_phb()
2637 * the PE number adjacent to the reserved one if possible. in pnv_pci_init_ioda_phb()
2664 pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", in pnv_pci_init_ioda_phb()
2688 * the child P2P bridges) can form individual PE. in pnv_pci_init_ioda_phb()