Lines Matching +full:disable +full:- +full:over +full:- +full:current
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * This file contains low-level cache management functions
5 * (In fact the only thing that is Apple-specific is that we assume
15 #include <asm/feature-fixups.h>
18 * Flush and disable all data caches (dL1, L2, L3). This is used
20 * or when "offlining" a CPU on SMP machines. This code is over
22 * bugs that I decided it was worth being over cautious
59 mtspr SPRN_HID0,r4 /* Disable DPM */
62 /* Disp-flush L1. We have a weird problem here that I never
64 * results in a non-working flush. We use that workaround for
65 * now until I finally understand what's going on. --BenH
84 /* Disable / invalidate / enable L1 data */
98 /* Get the current enable bit of the L2CR into r4 */
100 /* Set to data-only (pre-745x bit) */
113 1: /* disp-flush L2. The interesting thing here is that the L2 can be
115 * but that is probbaly fine. We disp-flush over 4Mb to be safe
134 /* now disable L2 */
149 /* Invalidate L2. This is pre-745x, we clear the L2I bit ourselves */
166 /* now disable the L1 data cache */
203 /* Disable L2 prefetching */
221 * with a dcbf loop over a few Mb to "help". The problem isn't totally
245 /* Flush and disable the L1 data cache */
299 1: mtspr SPRN_L2CR,r3 /* disable the L2 cache */
337 mtspr SPRN_L3CR,r3 /* disable the L3 cache */
347 6: mfspr r0,SPRN_HID0 /* now disable the L1 data cache */