Lines Matching +full:bus +full:- +full:addr
1 // SPDX-License-Identifier: GPL-2.0-or-later
19 #include <asm/pci-bridge.h>
22 #include <asm/ppc-pci.h>
23 #include <asm/isa-bridge.h>
37 for (; node; node = node->sibling) { in fixup_one_level_bus_range()
42 /* For PCI<->PCI bridges or CardBus bridges, we go down */ in fixup_one_level_bus_range()
43 class_code = of_get_property(node, "class-code", NULL); in fixup_one_level_bus_range()
47 bus_range = of_get_property(node, "bus-range", &len); in fixup_one_level_bus_range()
52 higher = fixup_one_level_bus_range(node->child, higher); in fixup_one_level_bus_range()
57 /* This routine fixes the "bus-range" property of all bridges in the
60 * Note that the bus numbers manipulated here are OF bus numbers, they
61 * are not Linux bus numbers.
69 /* Lookup the "bus-range" property for the hose */ in fixup_bus_range()
70 prop = of_find_property(bridge, "bus-range", &len); in fixup_bus_range()
71 if (prop == NULL || prop->value == NULL || len < 2 * sizeof(int)) { in fixup_bus_range()
72 printk(KERN_WARNING "Can't get bus-range for %pOF\n", in fixup_bus_range()
76 bus_range = prop->value; in fixup_bus_range()
77 bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]); in fixup_bus_range()
88 static unsigned long u3_agp_cfa1(u8 bus, u8 devfn, u8 off) in u3_agp_cfa1() argument
90 return ((unsigned long)bus << 16) | in u3_agp_cfa1()
97 u8 bus, u8 dev_fn, u8 offset) in u3_agp_cfg_access() argument
101 if (bus == hose->first_busno) { in u3_agp_cfg_access()
106 caddr = u3_agp_cfa1(bus, dev_fn, offset); in u3_agp_cfg_access()
110 out_le32(hose->cfg_addr, caddr); in u3_agp_cfg_access()
111 } while (in_le32(hose->cfg_addr) != caddr); in u3_agp_cfg_access()
114 return hose->cfg_data + offset; in u3_agp_cfg_access()
117 static int u3_agp_read_config(struct pci_bus *bus, unsigned int devfn, in u3_agp_read_config() argument
121 volatile void __iomem *addr; in u3_agp_read_config() local
123 hose = pci_bus_to_host(bus); in u3_agp_read_config()
127 addr = u3_agp_cfg_access(hose, bus->number, devfn, offset); in u3_agp_read_config()
128 if (!addr) in u3_agp_read_config()
136 *val = in_8(addr); in u3_agp_read_config()
139 *val = in_le16(addr); in u3_agp_read_config()
142 *val = in_le32(addr); in u3_agp_read_config()
148 static int u3_agp_write_config(struct pci_bus *bus, unsigned int devfn, in u3_agp_write_config() argument
152 volatile void __iomem *addr; in u3_agp_write_config() local
154 hose = pci_bus_to_host(bus); in u3_agp_write_config()
158 addr = u3_agp_cfg_access(hose, bus->number, devfn, offset); in u3_agp_write_config()
159 if (!addr) in u3_agp_write_config()
167 out_8(addr, val); in u3_agp_write_config()
170 out_le16(addr, val); in u3_agp_write_config()
173 out_le32(addr, val); in u3_agp_write_config()
190 static unsigned long u3_ht_cfa1(u8 bus, u8 devfn, u8 off) in u3_ht_cfa1() argument
192 return u3_ht_cfa0(devfn, off) + (bus << 16) + 0x01000000UL; in u3_ht_cfa1()
196 u8 bus, u8 devfn, u8 offset) in u3_ht_cfg_access() argument
198 if (bus == hose->first_busno) { in u3_ht_cfg_access()
201 return hose->cfg_data + u3_ht_cfa0(devfn, offset); in u3_ht_cfg_access()
203 return hose->cfg_data + u3_ht_cfa1(bus, devfn, offset); in u3_ht_cfg_access()
209 volatile void __iomem *addr; in u3_ht_root_read_config() local
211 addr = hose->cfg_addr; in u3_ht_root_read_config()
212 addr += ((offset & ~3) << 2) + (4 - len - (offset & 3)); in u3_ht_root_read_config()
216 *val = in_8(addr); in u3_ht_root_read_config()
219 *val = in_be16(addr); in u3_ht_root_read_config()
222 *val = in_be32(addr); in u3_ht_root_read_config()
232 volatile void __iomem *addr; in u3_ht_root_write_config() local
234 addr = hose->cfg_addr + ((offset & ~3) << 2) + (4 - len - (offset & 3)); in u3_ht_root_write_config()
241 out_8(addr, val); in u3_ht_root_write_config()
244 out_be16(addr, val); in u3_ht_root_write_config()
247 out_be32(addr, val); in u3_ht_root_write_config()
254 static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn, in u3_ht_read_config() argument
258 volatile void __iomem *addr; in u3_ht_read_config() local
260 hose = pci_bus_to_host(bus); in u3_ht_read_config()
264 if (bus->number == hose->first_busno && devfn == PCI_DEVFN(0, 0)) in u3_ht_read_config()
270 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset); in u3_ht_read_config()
271 if (!addr) in u3_ht_read_config()
280 *val = in_8(addr); in u3_ht_read_config()
283 *val = in_le16(addr); in u3_ht_read_config()
286 *val = in_le32(addr); in u3_ht_read_config()
292 static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn, in u3_ht_write_config() argument
296 volatile void __iomem *addr; in u3_ht_write_config() local
298 hose = pci_bus_to_host(bus); in u3_ht_write_config()
302 if (bus->number == hose->first_busno && devfn == PCI_DEVFN(0, 0)) in u3_ht_write_config()
308 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset); in u3_ht_write_config()
309 if (!addr) in u3_ht_write_config()
317 out_8(addr, val); in u3_ht_write_config()
320 out_le16(addr, val); in u3_ht_write_config()
323 out_le32(addr, val); in u3_ht_write_config()
343 static unsigned int u4_pcie_cfa1(unsigned int bus, unsigned int devfn, in u4_pcie_cfa1() argument
346 return (bus << 16) | in u4_pcie_cfa1()
353 u8 bus, u8 dev_fn, int offset) in u4_pcie_cfg_access() argument
357 if (bus == hose->first_busno) in u4_pcie_cfg_access()
360 caddr = u4_pcie_cfa1(bus, dev_fn, offset); in u4_pcie_cfg_access()
364 out_le32(hose->cfg_addr, caddr); in u4_pcie_cfg_access()
365 } while (in_le32(hose->cfg_addr) != caddr); in u4_pcie_cfg_access()
368 return hose->cfg_data + offset; in u4_pcie_cfg_access()
371 static int u4_pcie_read_config(struct pci_bus *bus, unsigned int devfn, in u4_pcie_read_config() argument
375 volatile void __iomem *addr; in u4_pcie_read_config() local
377 hose = pci_bus_to_host(bus); in u4_pcie_read_config()
382 addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset); in u4_pcie_read_config()
383 if (!addr) in u4_pcie_read_config()
391 *val = in_8(addr); in u4_pcie_read_config()
394 *val = in_le16(addr); in u4_pcie_read_config()
397 *val = in_le32(addr); in u4_pcie_read_config()
402 static int u4_pcie_write_config(struct pci_bus *bus, unsigned int devfn, in u4_pcie_write_config() argument
406 volatile void __iomem *addr; in u4_pcie_write_config() local
408 hose = pci_bus_to_host(bus); in u4_pcie_write_config()
413 addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset); in u4_pcie_write_config()
414 if (!addr) in u4_pcie_write_config()
422 out_8(addr, val); in u4_pcie_write_config()
425 out_le16(addr, val); in u4_pcie_write_config()
428 out_le32(addr, val); in u4_pcie_write_config()
442 /* On G5, we move AGP up to high bus number so we don't need in setup_u3_agp()
443 * to reassign bus numbers for HT. If we ever have P2P bridges in setup_u3_agp()
451 hose->first_busno = 0xf0; in setup_u3_agp()
452 hose->last_busno = 0xff; in setup_u3_agp()
453 hose->ops = &u3_agp_pci_ops; in setup_u3_agp()
454 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000); in setup_u3_agp()
455 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000); in setup_u3_agp()
462 /* We currently only implement the "non-atomic" config space, to in setup_u4_pcie()
465 hose->ops = &u4_pcie_pci_ops; in setup_u4_pcie()
466 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000); in setup_u4_pcie()
467 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000); in setup_u4_pcie()
474 hose->ops = &u3_ht_pci_ops; in setup_u3_ht()
480 hose->cfg_data = ioremap(0xf2000000, 0x02000000); in setup_u3_ht()
481 hose->cfg_addr = ioremap(0xf8070000, 0x1000); in setup_u3_ht()
483 hose->first_busno = 0; in setup_u3_ht()
484 hose->last_busno = 0xef; in setup_u3_ht()
499 bus_range = of_get_property(dev, "bus-range", &len); in maple_add_bridge()
501 printk(KERN_WARNING "Can't get bus-range for %pOF, assume bus 0\n", in maple_add_bridge()
507 return -ENOMEM; in maple_add_bridge()
508 hose->first_busno = bus_range ? bus_range[0] : 0; in maple_add_bridge()
509 hose->last_busno = bus_range ? bus_range[1] : 0xff; in maple_add_bridge()
510 hose->controller_ops = maple_pci_controller_ops; in maple_add_bridge()
513 if (of_device_is_compatible(dev, "u3-agp")) { in maple_add_bridge()
515 disp_name = "U3-AGP"; in maple_add_bridge()
517 } else if (of_device_is_compatible(dev, "u3-ht")) { in maple_add_bridge()
519 disp_name = "U3-HT"; in maple_add_bridge()
521 } else if (of_device_is_compatible(dev, "u4-pcie")) { in maple_add_bridge()
523 disp_name = "U4-PCIE"; in maple_add_bridge()
526 printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number: %d->%d\n", in maple_add_bridge()
527 disp_name, hose->first_busno, hose->last_busno); in maple_add_bridge()
533 /* Fixup "bus-range" OF property */ in maple_add_bridge()
548 DBG(" -> maple_pci_irq_fixup\n"); in maple_pci_irq_fixup()
551 if (u4_pcie != NULL && dev->bus->number == 0 && in maple_pci_irq_fixup()
552 pci_bus_to_host(dev->bus) == u4_pcie) { in maple_pci_irq_fixup()
554 dev->irq = irq_create_mapping(NULL, 1); in maple_pci_irq_fixup()
555 if (dev->irq) in maple_pci_irq_fixup()
556 irq_set_irq_type(dev->irq, IRQ_TYPE_LEVEL_LOW); in maple_pci_irq_fixup()
562 if (dev->vendor == PCI_VENDOR_ID_AMD && in maple_pci_irq_fixup()
563 dev->device == PCI_DEVICE_ID_AMD_8111_IDE && in maple_pci_irq_fixup()
564 (dev->class & 5) != 5) { in maple_pci_irq_fixup()
565 dev->irq = 0; in maple_pci_irq_fixup()
568 DBG(" <- maple_pci_irq_fixup\n"); in maple_pci_irq_fixup()
573 struct pci_controller *hose = pci_bus_to_host(bridge->bus); in maple_pci_root_bridge_prepare()
579 /* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We in maple_pci_root_bridge_prepare()
580 * assume there is no P2P bridge on the AGP bus, which should be a in maple_pci_root_bridge_prepare()
583 np = hose->dn; in maple_pci_root_bridge_prepare()
584 PCI_DN(np)->busno = 0xf0; in maple_pci_root_bridge_prepare()
586 PCI_DN(child)->busno = 0xf0; in maple_pci_root_bridge_prepare()
609 if ((of_device_is_compatible(np, "u4-pcie") || in maple_pci_init()
610 of_device_is_compatible(np, "u3-agp")) && in maple_pci_init()
614 if (of_device_is_compatible(np, "u3-ht")) { in maple_pci_init()
638 if (pdev->vendor != PCI_VENDOR_ID_AMD || in maple_pci_get_legacy_ide_irq()
639 pdev->device != PCI_DEVICE_ID_AMD_8111_IDE) in maple_pci_get_legacy_ide_irq()
664 dev->no_msi = 1; in quirk_ipr_msi()
665 dev_info(&dev->dev, "Quirk disabled MSI\n"); in quirk_ipr_msi()