79 void axon_msi_debug_setup(struct device_node *dn, struct axon_msic *msic);
82 					struct axon_msic *msic) { }  in axon_msi_debug_setup()  argument
86 static void msic_dcr_write(struct axon_msic *msic, unsigned int dcr_n, u32 val)  in msic_dcr_write()  argument
90 	dcr_write(msic->dcr_host, dcr_n, val);  in msic_dcr_write()
96 	struct axon_msic *msic = irq_desc_get_handler_data(desc);  in axon_msi_cascade()  local
101 	write_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG);  in axon_msi_cascade()
107 	while (msic->read_offset != write_offset && retry < 100) {  in axon_msi_cascade()
108 		idx  = msic->read_offset / sizeof(__le32);  in axon_msi_cascade()
109 		msi  = le32_to_cpu(msic->fifo_virt[idx]);  in axon_msi_cascade()
113 			  write_offset, msic->read_offset, msi);  in axon_msi_cascade()
115 		if (msi < nr_irqs && irq_get_chip_data(msi) == msic) {  in axon_msi_cascade()
117 			msic->fifo_virt[idx] = cpu_to_le32(0xffffffff);  in axon_msi_cascade()
137 		msic->read_offset += MSIC_FIFO_ENTRY_SIZE;  in axon_msi_cascade()
138 		msic->read_offset &= MSIC_FIFO_SIZE_MASK;  in axon_msi_cascade()
144 		msic->read_offset += MSIC_FIFO_ENTRY_SIZE;  in axon_msi_cascade()
145 		msic->read_offset &= MSIC_FIFO_SIZE_MASK;  in axon_msi_cascade()
156 	struct axon_msic *msic = NULL;  in find_msi_translator()  local
192 	msic = irq_domain->host_data;  in find_msi_translator()
197 	return msic;  in find_msi_translator()
257 	struct axon_msic *msic;  in axon_msi_setup_msi_irqs()  local
259 	msic = find_msi_translator(dev);  in axon_msi_setup_msi_irqs()
260 	if (!msic)  in axon_msi_setup_msi_irqs()
268 		virq = irq_create_direct_mapping(msic->irq_domain);  in axon_msi_setup_msi_irqs()
319 	struct axon_msic *msic = dev_get_drvdata(&device->dev);  in axon_msi_shutdown()  local
323 		 irq_domain_get_of_node(msic->irq_domain));  in axon_msi_shutdown()
324 	tmp  = dcr_read(msic->dcr_host, MSIC_CTRL_REG);  in axon_msi_shutdown()
326 	msic_dcr_write(msic, MSIC_CTRL_REG, tmp);  in axon_msi_shutdown()
332 	struct axon_msic *msic;  in axon_msi_probe()  local
338 	msic = kzalloc(sizeof(*msic), GFP_KERNEL);  in axon_msi_probe()
339 	if (!msic) {  in axon_msi_probe()
355 	msic->dcr_host = dcr_map(dn, dcr_base, dcr_len);  in axon_msi_probe()
356 	if (!DCR_MAP_OK(msic->dcr_host)) {  in axon_msi_probe()
362 	msic->fifo_virt = dma_alloc_coherent(&device->dev, MSIC_FIFO_SIZE_BYTES,  in axon_msi_probe()
363 					     &msic->fifo_phys, GFP_KERNEL);  in axon_msi_probe()
364 	if (!msic->fifo_virt) {  in axon_msi_probe()
376 	memset(msic->fifo_virt, 0xff, MSIC_FIFO_SIZE_BYTES);  in axon_msi_probe()
379 	msic->irq_domain = irq_domain_add_nomap(dn, 65536, &msic_host_ops, msic);  in axon_msi_probe()
380 	if (!msic->irq_domain) {  in axon_msi_probe()
386 	irq_set_handler_data(virq, msic);  in axon_msi_probe()
391 	msic_dcr_write(msic, MSIC_BASE_ADDR_HI_REG, msic->fifo_phys >> 32);  in axon_msi_probe()
392 	msic_dcr_write(msic, MSIC_BASE_ADDR_LO_REG,  in axon_msi_probe()
393 				  msic->fifo_phys & 0xFFFFFFFF);  in axon_msi_probe()
394 	msic_dcr_write(msic, MSIC_CTRL_REG,  in axon_msi_probe()
398 	msic->read_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG)  in axon_msi_probe()
401 	dev_set_drvdata(&device->dev, msic);  in axon_msi_probe()
406 	axon_msi_debug_setup(dn, msic);  in axon_msi_probe()
413 	dma_free_coherent(&device->dev, MSIC_FIFO_SIZE_BYTES, msic->fifo_virt,  in axon_msi_probe()
414 			  msic->fifo_phys);  in axon_msi_probe()
416 	kfree(msic);  in axon_msi_probe()
448 	struct axon_msic *msic = data;  in msic_set()  local
449 	out_le32(msic->trigger, val);  in msic_set()
461 void axon_msi_debug_setup(struct device_node *dn, struct axon_msic *msic)  in axon_msi_debug_setup()  argument
471 	msic->trigger = ioremap(res.start, 0x4);  in axon_msi_debug_setup()
472 	if (!msic->trigger) {  in axon_msi_debug_setup()
479 	debugfs_create_file(name, 0600, arch_debugfs_dir, msic, &fops_msic);  in axon_msi_debug_setup()