8  * This file is a driver for the General Purpose Timer (gpt) devices
14  * This driver supports the GPIO and IRQ controller functions of the GPT
18  * this prevents the use of any gpt0 gpt function (i.e. they will fail with
19  * -EBUSY).  Thus, the safety wdt function always has precedence over the gpt
25  * to the device tree node for the gpt device (typically in the .dts file
33  * be added to the device tree node for the gpt device:
38  * the IRQ number because the GPT only has a single IRQ source.  For flags,
72 MODULE_DESCRIPTION("Freescale MPC52xx gpt driver");
77  * struct mpc52xx_gpt - Private data structure for MPC52xx GPT driver
79  * @regs: virtual address of GPT registers
84  *   if the gpt may be used as wdt, bit 1 (MPC52xx_GPT_IS_WDT) indicates
85  *   if the timer is actively used as wdt which blocks gpt functions
88 	struct list_head list;		/* List of all GPT devices */
139 	struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d);  in mpc52xx_gpt_irq_unmask()  local
142 	raw_spin_lock_irqsave(&gpt->lock, flags);  in mpc52xx_gpt_irq_unmask()
143 	setbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);  in mpc52xx_gpt_irq_unmask()
144 	raw_spin_unlock_irqrestore(&gpt->lock, flags);  in mpc52xx_gpt_irq_unmask()
149 	struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d);  in mpc52xx_gpt_irq_mask()  local
152 	raw_spin_lock_irqsave(&gpt->lock, flags);  in mpc52xx_gpt_irq_mask()
153 	clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);  in mpc52xx_gpt_irq_mask()
154 	raw_spin_unlock_irqrestore(&gpt->lock, flags);  in mpc52xx_gpt_irq_mask()
159 	struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d);  in mpc52xx_gpt_irq_ack()  local
161 	out_be32(&gpt->regs->status, MPC52xx_GPT_STATUS_IRQMASK);  in mpc52xx_gpt_irq_ack()
166 	struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d);  in mpc52xx_gpt_irq_set_type()  local
170 	dev_dbg(gpt->dev, "%s: virq=%i type=%x\n", __func__, d->irq, flow_type);  in mpc52xx_gpt_irq_set_type()
172 	raw_spin_lock_irqsave(&gpt->lock, flags);  in mpc52xx_gpt_irq_set_type()
173 	reg = in_be32(&gpt->regs->mode) & ~MPC52xx_GPT_MODE_ICT_MASK;  in mpc52xx_gpt_irq_set_type()
178 	out_be32(&gpt->regs->mode, reg);  in mpc52xx_gpt_irq_set_type()
179 	raw_spin_unlock_irqrestore(&gpt->lock, flags);  in mpc52xx_gpt_irq_set_type()
185 	.name = "MPC52xx GPT",
194 	struct mpc52xx_gpt_priv *gpt = irq_desc_get_handler_data(desc);  in mpc52xx_gpt_irq_cascade()  local
197 	status = in_be32(&gpt->regs->status) & MPC52xx_GPT_STATUS_IRQMASK;  in mpc52xx_gpt_irq_cascade()
199 		generic_handle_domain_irq(gpt->irqhost, 0);  in mpc52xx_gpt_irq_cascade()
205 	struct mpc52xx_gpt_priv *gpt = h->host_data;  in mpc52xx_gpt_irq_map()  local
207 	dev_dbg(gpt->dev, "%s: h=%p, virq=%i\n", __func__, h, virq);  in mpc52xx_gpt_irq_map()
208 	irq_set_chip_data(virq, gpt);  in mpc52xx_gpt_irq_map()
219 	struct mpc52xx_gpt_priv *gpt = h->host_data;  in mpc52xx_gpt_irq_xlate()  local
221 	dev_dbg(gpt->dev, "%s: flags=%i\n", __func__, intspec[0]);  in mpc52xx_gpt_irq_xlate()
224 		dev_err(gpt->dev, "bad irq specifier in %pOF\n", ct);  in mpc52xx_gpt_irq_xlate()
228 	*out_hwirq = 0; /* The GPT only has 1 IRQ line */  in mpc52xx_gpt_irq_xlate()
240 mpc52xx_gpt_irq_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node)  in mpc52xx_gpt_irq_setup()  argument
250 	gpt->irqhost = irq_domain_create_linear(of_fwnode_handle(node), 1, &mpc52xx_gpt_irq_ops, gpt);  in mpc52xx_gpt_irq_setup()
251 	if (!gpt->irqhost) {  in mpc52xx_gpt_irq_setup()
252 		dev_err(gpt->dev, "irq_domain_create_linear() failed\n");  in mpc52xx_gpt_irq_setup()
256 	irq_set_handler_data(cascade_virq, gpt);  in mpc52xx_gpt_irq_setup()
259 	/* If the GPT is currently disabled, then change it to be in Input  in mpc52xx_gpt_irq_setup()
262 	raw_spin_lock_irqsave(&gpt->lock, flags);  in mpc52xx_gpt_irq_setup()
263 	mode = in_be32(&gpt->regs->mode);  in mpc52xx_gpt_irq_setup()
265 		out_be32(&gpt->regs->mode, mode | MPC52xx_GPT_MODE_MS_IC);  in mpc52xx_gpt_irq_setup()
266 	raw_spin_unlock_irqrestore(&gpt->lock, flags);  in mpc52xx_gpt_irq_setup()
268 	dev_dbg(gpt->dev, "%s() complete. virq=%i\n", __func__, cascade_virq);  in mpc52xx_gpt_irq_setup()
278 	struct mpc52xx_gpt_priv *gpt = gpiochip_get_data(gc);  in mpc52xx_gpt_gpio_get()  local
280 	return (in_be32(&gpt->regs->status) >> 8) & 1;  in mpc52xx_gpt_gpio_get()
286 	struct mpc52xx_gpt_priv *gpt = gpiochip_get_data(gc);  in mpc52xx_gpt_gpio_set()  local
290 	dev_dbg(gpt->dev, "%s: gpio:%d v:%d\n", __func__, gpio, v);  in mpc52xx_gpt_gpio_set()
293 	raw_spin_lock_irqsave(&gpt->lock, flags);  in mpc52xx_gpt_gpio_set()
294 	clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK, r);  in mpc52xx_gpt_gpio_set()
295 	raw_spin_unlock_irqrestore(&gpt->lock, flags);  in mpc52xx_gpt_gpio_set()
302 	struct mpc52xx_gpt_priv *gpt = gpiochip_get_data(gc);  in mpc52xx_gpt_gpio_dir_in()  local
305 	dev_dbg(gpt->dev, "%s: gpio:%d\n", __func__, gpio);  in mpc52xx_gpt_gpio_dir_in()
307 	raw_spin_lock_irqsave(&gpt->lock, flags);  in mpc52xx_gpt_gpio_dir_in()
308 	clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK);  in mpc52xx_gpt_gpio_dir_in()
309 	raw_spin_unlock_irqrestore(&gpt->lock, flags);  in mpc52xx_gpt_gpio_dir_in()
321 static void mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv *gpt)  in mpc52xx_gpt_gpio_setup()  argument
325 	/* Only setup GPIO if the device claims the GPT is a GPIO controller */  in mpc52xx_gpt_gpio_setup()
326 	if (!device_property_present(gpt->dev, "gpio-controller"))  in mpc52xx_gpt_gpio_setup()
329 	gpt->gc.label = kasprintf(GFP_KERNEL, "%pfw", dev_fwnode(gpt->dev));  in mpc52xx_gpt_gpio_setup()
330 	if (!gpt->gc.label) {  in mpc52xx_gpt_gpio_setup()
331 		dev_err(gpt->dev, "out of memory\n");  in mpc52xx_gpt_gpio_setup()
335 	gpt->gc.ngpio = 1;  in mpc52xx_gpt_gpio_setup()
336 	gpt->gc.direction_input  = mpc52xx_gpt_gpio_dir_in;  in mpc52xx_gpt_gpio_setup()
337 	gpt->gc.direction_output = mpc52xx_gpt_gpio_dir_out;  in mpc52xx_gpt_gpio_setup()
338 	gpt->gc.get = mpc52xx_gpt_gpio_get;  in mpc52xx_gpt_gpio_setup()
339 	gpt->gc.set = mpc52xx_gpt_gpio_set;  in mpc52xx_gpt_gpio_setup()
340 	gpt->gc.base = -1;  in mpc52xx_gpt_gpio_setup()
341 	gpt->gc.parent = gpt->dev;  in mpc52xx_gpt_gpio_setup()
344 	clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_MS_MASK,  in mpc52xx_gpt_gpio_setup()
347 	rc = gpiochip_add_data(&gpt->gc, gpt);  in mpc52xx_gpt_gpio_setup()
349 		dev_err(gpt->dev, "gpiochip_add_data() failed; rc=%i\n", rc);  in mpc52xx_gpt_gpio_setup()
351 	dev_dbg(gpt->dev, "%s() complete.\n", __func__);  in mpc52xx_gpt_gpio_setup()
354 static void mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv *gpt) { }  in mpc52xx_gpt_gpio_setup()  argument
362  * mpc52xx_gpt_from_irq - Return the GPT device associated with an IRQ number
367 	struct mpc52xx_gpt_priv *gpt;  in mpc52xx_gpt_from_irq()  local
373 		gpt = container_of(pos, struct mpc52xx_gpt_priv, list);  in mpc52xx_gpt_from_irq()
374 		if (gpt->irqhost && irq == irq_find_mapping(gpt->irqhost, 0)) {  in mpc52xx_gpt_from_irq()
376 			return gpt;  in mpc52xx_gpt_from_irq()
385 static int mpc52xx_gpt_do_start(struct mpc52xx_gpt_priv *gpt, u64 period,  in mpc52xx_gpt_do_start()  argument
405 	clocks = period * (u64)gpt->ipb_freq;  in mpc52xx_gpt_do_start()
432 	/* Set and enable the timer, reject an attempt to use a wdt as gpt */  in mpc52xx_gpt_do_start()
433 	raw_spin_lock_irqsave(&gpt->lock, flags);  in mpc52xx_gpt_do_start()
435 		gpt->wdt_mode |= MPC52xx_GPT_IS_WDT;  in mpc52xx_gpt_do_start()
436 	else if ((gpt->wdt_mode & MPC52xx_GPT_IS_WDT) != 0) {  in mpc52xx_gpt_do_start()
437 		raw_spin_unlock_irqrestore(&gpt->lock, flags);  in mpc52xx_gpt_do_start()
440 	out_be32(&gpt->regs->count, prescale << 16 | clocks);  in mpc52xx_gpt_do_start()
441 	clrsetbits_be32(&gpt->regs->mode, clear, set);  in mpc52xx_gpt_do_start()
442 	raw_spin_unlock_irqrestore(&gpt->lock, flags);  in mpc52xx_gpt_do_start()
448  * mpc52xx_gpt_start_timer - Set and enable the GPT timer
449  * @gpt: Pointer to gpt private data structure
455 int mpc52xx_gpt_start_timer(struct mpc52xx_gpt_priv *gpt, u64 period,  in mpc52xx_gpt_start_timer()  argument
458 	return mpc52xx_gpt_do_start(gpt, period, continuous, 0);  in mpc52xx_gpt_start_timer()
463  * mpc52xx_gpt_stop_timer - Stop a gpt
464  * @gpt: Pointer to gpt private data structure
468 int mpc52xx_gpt_stop_timer(struct mpc52xx_gpt_priv *gpt)  in mpc52xx_gpt_stop_timer()  argument
472 	/* reject the operation if the timer is used as watchdog (gpt 0 only) */  in mpc52xx_gpt_stop_timer()
473 	raw_spin_lock_irqsave(&gpt->lock, flags);  in mpc52xx_gpt_stop_timer()
474 	if ((gpt->wdt_mode & MPC52xx_GPT_IS_WDT) != 0) {  in mpc52xx_gpt_stop_timer()
475 		raw_spin_unlock_irqrestore(&gpt->lock, flags);  in mpc52xx_gpt_stop_timer()
479 	clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_COUNTER_ENABLE);  in mpc52xx_gpt_stop_timer()
480 	raw_spin_unlock_irqrestore(&gpt->lock, flags);  in mpc52xx_gpt_stop_timer()
487  * @gpt: Pointer to gpt private data structure
491 u64 mpc52xx_gpt_timer_period(struct mpc52xx_gpt_priv *gpt)  in mpc52xx_gpt_timer_period()  argument
497 	raw_spin_lock_irqsave(&gpt->lock, flags);  in mpc52xx_gpt_timer_period()
498 	period = in_be32(&gpt->regs->count);  in mpc52xx_gpt_timer_period()
499 	raw_spin_unlock_irqrestore(&gpt->lock, flags);  in mpc52xx_gpt_timer_period()
506 	do_div(period, gpt->ipb_freq);  in mpc52xx_gpt_timer_period()
521 /* wdt-capable gpt */
675 static int mpc52xx_gpt_wdt_setup(struct mpc52xx_gpt_priv *gpt,  in mpc52xx_gpt_wdt_setup()  argument
680 	/* remember the gpt for the wdt operation */  in mpc52xx_gpt_wdt_setup()
681 	mpc52xx_gpt_wdt = gpt;  in mpc52xx_gpt_wdt_setup()
688 	if (mpc52xx_gpt_do_start(gpt, real_timeout, 0, 1))  in mpc52xx_gpt_wdt_setup()
689 		dev_warn(gpt->dev, "starting as wdt failed\n");  in mpc52xx_gpt_wdt_setup()
691 		dev_info(gpt->dev, "watchdog set to %us timeout\n", *period);  in mpc52xx_gpt_wdt_setup()
702 static inline int mpc52xx_gpt_wdt_setup(struct mpc52xx_gpt_priv *gpt,  in mpc52xx_gpt_wdt_setup()  argument
715 	struct mpc52xx_gpt_priv *gpt;  in mpc52xx_gpt_probe()  local
717 	gpt = devm_kzalloc(&ofdev->dev, sizeof *gpt, GFP_KERNEL);  in mpc52xx_gpt_probe()
718 	if (!gpt)  in mpc52xx_gpt_probe()
721 	raw_spin_lock_init(&gpt->lock);  in mpc52xx_gpt_probe()
722 	gpt->dev = &ofdev->dev;  in mpc52xx_gpt_probe()
723 	gpt->ipb_freq = mpc5xxx_get_bus_frequency(&ofdev->dev);  in mpc52xx_gpt_probe()
724 	gpt->regs = of_iomap(ofdev->dev.of_node, 0);  in mpc52xx_gpt_probe()
725 	if (!gpt->regs)  in mpc52xx_gpt_probe()
728 	dev_set_drvdata(&ofdev->dev, gpt);  in mpc52xx_gpt_probe()
730 	mpc52xx_gpt_gpio_setup(gpt);  in mpc52xx_gpt_probe()
731 	mpc52xx_gpt_irq_setup(gpt, ofdev->dev.of_node);  in mpc52xx_gpt_probe()
734 	list_add(&gpt->list, &mpc52xx_gpt_list);  in mpc52xx_gpt_probe()
742 		gpt->wdt_mode = MPC52xx_GPT_CAN_WDT;  in mpc52xx_gpt_probe()
746 			dev_info(gpt->dev, "used as watchdog\n");  in mpc52xx_gpt_probe()
747 			gpt->wdt_mode |= MPC52xx_GPT_IS_WDT;  in mpc52xx_gpt_probe()
749 			dev_info(gpt->dev, "can function as watchdog\n");  in mpc52xx_gpt_probe()
750 		mpc52xx_gpt_wdt_setup(gpt, on_boot_wdt);  in mpc52xx_gpt_probe()
757 	{ .compatible = "fsl,mpc5200-gpt", },
760 	{ .compatible = "fsl,mpc5200-gpt-gpio", },
761 	{ .compatible = "mpc5200-gpt", },
767 		.name = "mpc52xx-gpt",