408  * - receives the "bus frequency" from the caller (that's the IPS clock
411  *   IPS divider value from hardware
414  *   IPS bus clock (supported for backwards compatibility, such that
418  *   SYS -> CSB -> IPS) from the REF clock rate and the returned mul/div
439 	 * IPS rate), or backtrack from IPS and multiplier values that  in mpc512x_clk_setup_ref_clock()
456 		calc_freq = bus_freq;	/* start with IPS */  in mpc512x_clk_setup_ref_clock()
457 		calc_freq *= *ips_div;	/* IPS -> CSB */  in mpc512x_clk_setup_ref_clock()
638 	 * "MCLK <= IPS" constraint, the fixed divider value of 1  in mpc512x_clk_setup_mclk()
640 	 * CSB which is greater than IPS; the serial port setup may have  in mpc512x_clk_setup_mclk()
646 	 * - MCLK DIV such to not exceed the IPS clock  in mpc512x_clk_setup_mclk()
734 	/* now setup the REF -> SYS -> CSB -> IPS hierarchy */  in mpc512x_clk_setup_clock_tree()
738 	clks[MPC512x_CLK_IPS] = mpc512x_clk_divtable("ips", "csb",  in mpc512x_clk_setup_clock_tree()
741 	/* now setup anything below SYS and CSB and IPS */  in mpc512x_clk_setup_clock_tree()
805 				"nfc-ug", "ips", &clkregs->scfr1,  in mpc512x_clk_setup_clock_tree()
808 	clks[MPC512x_CLK_LPC_UG] = mpc512x_clk_divtable("lpc-ug", "ips",  in mpc512x_clk_setup_clock_tree()
818 				"pata", "ips", &clkregs->sccr1, 28);  in mpc512x_clk_setup_clock_tree()
825 				name, "ips", &clkregs->sccr1, 27 - mclk_idx);  in mpc512x_clk_setup_clock_tree()
828 	clks[MPC512x_CLK_PSC_FIFO] = mpc512x_clk_gated("psc-fifo", "ips",  in mpc512x_clk_setup_clock_tree()
832 				"sata", "ips", &clkregs->sccr1, 14);  in mpc512x_clk_setup_clock_tree()
834 	clks[MPC512x_CLK_FEC] = mpc512x_clk_gated("fec", "ips",  in mpc512x_clk_setup_clock_tree()
844 				"fec2", "ips", &clkregs->sccr1, 9);  in mpc512x_clk_setup_clock_tree()
853 	clks[MPC512x_CLK_MEM] = mpc512x_clk_gated("mem", "ips",  in mpc512x_clk_setup_clock_tree()
859 	clks[MPC512x_CLK_I2C] = mpc512x_clk_gated("i2c", "ips",  in mpc512x_clk_setup_clock_tree()
862 	clks[MPC512x_CLK_BDLC] = mpc512x_clk_gated("bdlc", "ips",  in mpc512x_clk_setup_clock_tree()
871 				"spdif", "ips", &clkregs->sccr2, 23);  in mpc512x_clk_setup_clock_tree()
1064 	 * do register the 'ips', 'sys', and 'ref' names globally  in mpc5121_clk_provide_backwards_compat()
1069 		clk_register_clkdev(clks[MPC512x_CLK_IPS], "ips", NULL);  in mpc5121_clk_provide_backwards_compat()
1205 	 * a REF root that was created from the IPS bus clock input  in mpc5121_clk_init()