Lines Matching +full:1 +full:c
43 * [ ] [ sample ] [cache] [ pmc ] [unit ] c m [ pmcxsel ]
74 * MMCRC[53:55] = cache_sel[1:3] (L2EVENT_SEL)
77 * MMCRC[47:49] = cache_sel[1:3] (L3EVENT_SEL0)
78 * else if cache_sel[0] == 1:
80 * else if cache_sel[1]: # L1 event
85 * MMCRA[63] = 1 (SAMPLE_ENABLE)
234 return -1; in power8_bhrb_filter_map()
237 return -1; in power8_bhrb_filter_map()
240 return -1; in power8_bhrb_filter_map()
248 return -1; in power8_bhrb_filter_map()
259 #define C(x) PERF_COUNT_HW_CACHE_##x macro
263 * 0 means not supported, -1 means nonsensical, other values
266 static u64 power8_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
267 [ C(L1D) ] = {
268 [ C(OP_READ) ] = {
269 [ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
270 [ C(RESULT_MISS) ] = PM_LD_MISS_L1,
272 [ C(OP_WRITE) ] = {
273 [ C(RESULT_ACCESS) ] = 0,
274 [ C(RESULT_MISS) ] = PM_ST_MISS_L1,
276 [ C(OP_PREFETCH) ] = {
277 [ C(RESULT_ACCESS) ] = PM_L1_PREF,
278 [ C(RESULT_MISS) ] = 0,
281 [ C(L1I) ] = {
282 [ C(OP_READ) ] = {
283 [ C(RESULT_ACCESS) ] = PM_INST_FROM_L1,
284 [ C(RESULT_MISS) ] = PM_L1_ICACHE_MISS,
286 [ C(OP_WRITE) ] = {
287 [ C(RESULT_ACCESS) ] = PM_L1_DEMAND_WRITE,
288 [ C(RESULT_MISS) ] = -1,
290 [ C(OP_PREFETCH) ] = {
291 [ C(RESULT_ACCESS) ] = PM_IC_PREF_WRITE,
292 [ C(RESULT_MISS) ] = 0,
295 [ C(LL) ] = {
296 [ C(OP_READ) ] = {
297 [ C(RESULT_ACCESS) ] = PM_DATA_FROM_L3,
298 [ C(RESULT_MISS) ] = PM_DATA_FROM_L3MISS,
300 [ C(OP_WRITE) ] = {
301 [ C(RESULT_ACCESS) ] = PM_L2_ST,
302 [ C(RESULT_MISS) ] = PM_L2_ST_MISS,
304 [ C(OP_PREFETCH) ] = {
305 [ C(RESULT_ACCESS) ] = PM_L3_PREF_ALL,
306 [ C(RESULT_MISS) ] = 0,
309 [ C(DTLB) ] = {
310 [ C(OP_READ) ] = {
311 [ C(RESULT_ACCESS) ] = 0,
312 [ C(RESULT_MISS) ] = PM_DTLB_MISS,
314 [ C(OP_WRITE) ] = {
315 [ C(RESULT_ACCESS) ] = -1,
316 [ C(RESULT_MISS) ] = -1,
318 [ C(OP_PREFETCH) ] = {
319 [ C(RESULT_ACCESS) ] = -1,
320 [ C(RESULT_MISS) ] = -1,
323 [ C(ITLB) ] = {
324 [ C(OP_READ) ] = {
325 [ C(RESULT_ACCESS) ] = 0,
326 [ C(RESULT_MISS) ] = PM_ITLB_MISS,
328 [ C(OP_WRITE) ] = {
329 [ C(RESULT_ACCESS) ] = -1,
330 [ C(RESULT_MISS) ] = -1,
332 [ C(OP_PREFETCH) ] = {
333 [ C(RESULT_ACCESS) ] = -1,
334 [ C(RESULT_MISS) ] = -1,
337 [ C(BPU) ] = {
338 [ C(OP_READ) ] = {
339 [ C(RESULT_ACCESS) ] = PM_BRU_FIN,
340 [ C(RESULT_MISS) ] = PM_BR_MPRED_CMPL,
342 [ C(OP_WRITE) ] = {
343 [ C(RESULT_ACCESS) ] = -1,
344 [ C(RESULT_MISS) ] = -1,
346 [ C(OP_PREFETCH) ] = {
347 [ C(RESULT_ACCESS) ] = -1,
348 [ C(RESULT_MISS) ] = -1,
351 [ C(NODE) ] = {
352 [ C(OP_READ) ] = {
353 [ C(RESULT_ACCESS) ] = -1,
354 [ C(RESULT_MISS) ] = -1,
356 [ C(OP_WRITE) ] = {
357 [ C(RESULT_ACCESS) ] = -1,
358 [ C(RESULT_MISS) ] = -1,
360 [ C(OP_PREFETCH) ] = {
361 [ C(RESULT_ACCESS) ] = -1,
362 [ C(RESULT_MISS) ] = -1,
367 #undef C
372 .max_alternatives = MAX_ALT + 1,