35 #define PM_IDU		4
88  *     48-50: number of events needing PMC1-4 0x0007_0000_0000_0000
109  *     28-29: count of events needing PMC3/4 0x3000_0000
153 		if (pmc <= 4)  in power5_get_constraint()
167 		if (byte >= 4) {  in power5_get_constraint()
170 			/* Map LSU1 low word (bytes 4-7) to unit LSU1+1 */  in power5_get_constraint()
184 		 * on PMC1/2; bytes 1 and 3 on PMC3/4.  in power5_get_constraint()
189 		mask  |= 0xfUL << (24 - 4 * byte);  in power5_get_constraint()
190 		value |= (unsigned long)unit << (24 - 4 * byte);  in power5_get_constraint()
197 		/* increment PMC3/4 field */  in power5_get_constraint()
202 		/* need a counter from PMC1-4 set */  in power5_get_constraint()
239 static const unsigned char bytedecode_alternatives[4][4] = {
243 	/* PMC 4 */	{ 0x07, 0x17, 0x0e, 0x1e }
256 	if (pmc == 0 || pmc > 4)  in find_alternative_bdecode()
258 	altpmc = 5 - pmc;	/* 1 <-> 4, 2 <-> 3 */  in find_alternative_bdecode()
260 	for (j = 0; j < 4; ++j) {  in find_alternative_bdecode()
309 	0,	/* 0c */
355 			bit = 4;  in power5_marked_instr_event()
359 			bit = 4 - pmc;  in power5_marked_instr_event()
361 			bit = 4;  in power5_marked_instr_event()
371 		/* byte 1 bits 0-7, byte 2 bits 0,2-4,6 */  in power5_marked_instr_event()
373 	} else if (unit == PM_LSU1 && byte >= 4) {  in power5_marked_instr_event()
374 		byte -= 4;  in power5_marked_instr_event()
375 		/* byte 4 bits 1,3,5,7, byte 5 bits 6-7, byte 7 bits 0-4,6 */  in power5_marked_instr_event()
395 	unsigned char busbyte[4];  in power5_compute_mmcr()
414 			/* count 1/2 vs 3/4 use */  in power5_compute_mmcr()
415 			if (pmc <= 4)  in power5_compute_mmcr()
425 			if (byte >= 4) {  in power5_compute_mmcr()
474 	for (byte = 0; byte < 4; ++byte) {  in power5_compute_mmcr()
499 			for (pmc = 0; pmc < 4; ++pmc) {  in power5_compute_mmcr()
512 		} else if (pmc <= 4) {  in power5_compute_mmcr()
560 #define C(x)	PERF_COUNT_HW_CACHE_##x  macro
567 static u64 power5_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
568 	[C(L1D)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
569 		[C(OP_READ)] = {	0x4c1090,	0x3c1088	},
570 		[C(OP_WRITE)] = {	0x3c1090,	0xc10c3		},
571 		[C(OP_PREFETCH)] = {	0xc70e7,	0		},
573 	[C(L1I)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
574 		[C(OP_READ)] = {	0,		0		},
575 		[C(OP_WRITE)] = {	-1,		-1		},
576 		[C(OP_PREFETCH)] = {	0,		0		},
578 	[C(LL)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
579 		[C(OP_READ)] = {	0,		0x3c309b	},
580 		[C(OP_WRITE)] = {	0,		0		},
581 		[C(OP_PREFETCH)] = {	0xc50c3,	0		},
583 	[C(DTLB)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
584 		[C(OP_READ)] = {	0x2c4090,	0x800c4		},
585 		[C(OP_WRITE)] = {	-1,		-1		},
586 		[C(OP_PREFETCH)] = {	-1,		-1		},
588 	[C(ITLB)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
589 		[C(OP_READ)] = {	0,		0x800c0		},
590 		[C(OP_WRITE)] = {	-1,		-1		},
591 		[C(OP_PREFETCH)] = {	-1,		-1		},
593 	[C(BPU)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
594 		[C(OP_READ)] = {	0x230e4,	0x230e5		},
595 		[C(OP_WRITE)] = {	-1,		-1		},
596 		[C(OP_PREFETCH)] = {	-1,		-1		},
598 	[C(NODE)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
599 		[C(OP_READ)] = {	-1,		-1		},
600 		[C(OP_WRITE)] = {	-1,		-1		},
601 		[C(OP_PREFETCH)] = {	-1,		-1		},