1 // SPDX-License-Identifier: GPL-2.0-or-later
18 #define PM_PMC_SH	20	/* PMC number (1-based) for direct events */
21 #define PM_UNIT_SH	16	/* TTMMUX number and setting - unit select */
23 #define PM_BYTE_SH	12	/* Byte number of event bus to use */
34 #define PM_ISU1		3
49 #define MMCR1_TTMSEL_MSK	3
55 #define MMCR1_GRS_L2SEL_MSK	3
57 #define MMCR1_GRS_L3SEL_MSK	3
61 #define MMCR1_GRS_FABSEL_MSK	3
70 #define MMCR1_PMCSEL_SH(n)	(MMCR1_PMC1SEL_SH - (n) * 8)
80  * T0 - TTM0 constraint
81  *     54-55: TTM0SEL value (0=FPU, 2=IFU, 3=ISU1) 0xc0_0000_0000_0000
83  * T1 - TTM1 constraint
84  *     52-53: TTM1SEL value (0=IDU, 3=GRS) 0x30_0000_0000_0000
86  * NC - number of counters
88  *     48-50: number of events needing PMC1-4 0x0007_0000_0000_0000
90  * G0..G3 - GRS mux constraints
91  *     46-47: GRS_L2SEL value
92  *     44-45: GRS_L3SEL value
93  *     41-44: GRS_MCSEL value
94  *     39-40: GRS_FABSEL value
97  * UC - unit constraint: can't have all three of FPU|IFU|ISU1, ISU0, IDU|GRS
105  *     31-32: count of events needing PMC1/2 0x1_8000_0000
109  *     28-29: count of events needing PMC3/4 0x3000_0000
112  *     24-27: Byte 0 event source 0x0f00_0000
116  *     20-23, 16-19, 12-15: Byte 1, 2, 3 event sources
119  *     0-11: Count of events needing PMC1..PMC6
141 	int pmc, byte, unit, sh;  in power5_get_constraint()  local
144 	int grp = -1;  in power5_get_constraint()
149 			return -1;  in power5_get_constraint()
150 		sh = (pmc - 1) * 2;  in power5_get_constraint()
154 			grp = (pmc - 1) >> 1;  in power5_get_constraint()
156 			return -1;  in power5_get_constraint()
161 			return -1;  in power5_get_constraint()
166 		byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;  in power5_get_constraint()
167 		if (byte >= 4) {  in power5_get_constraint()
169 				return -1;  in power5_get_constraint()
170 			/* Map LSU1 low word (bytes 4-7) to unit LSU1+1 */  in power5_get_constraint()
172 			byte &= 3;  in power5_get_constraint()
176 			fmask = (bit == 6)? 7: 3;  in power5_get_constraint()
184 		 * on PMC1/2; bytes 1 and 3 on PMC3/4.  in power5_get_constraint()
187 			grp = byte & 1;  in power5_get_constraint()
188 		/* Set byte lane select field */  in power5_get_constraint()
189 		mask  |= 0xfUL << (24 - 4 * byte);  in power5_get_constraint()
190 		value |= (unsigned long)unit << (24 - 4 * byte);  in power5_get_constraint()
202 		/* need a counter from PMC1-4 set */  in power5_get_constraint()
211 #define MAX_ALT	3	/* at most 3 alternatives for any event */
223  * index into the alternatives table if found, else -1.
236 	return -1;  in find_alternative()
242 	/* PMC 3 */	{ 0x20, 0x22, 0x24, 0x26 },
247  * Some direct events for decodes of event bus byte 3 have alternative
249  * event code for those that do, or -1 otherwise.
257 		return -1;  in find_alternative_bdecode()
258 	altpmc = 5 - pmc;	/* 1 <-> 4, 2 <-> 3 */  in find_alternative_bdecode()
261 		if (bytedecode_alternatives[pmc - 1][j] == pp) {  in find_alternative_bdecode()
264 				bytedecode_alternatives[altpmc - 1][j];  in find_alternative_bdecode()
267 	return -1;  in find_alternative_bdecode()
296  * The 0x80 bit indicates a byte decode PMCSEL value.
307 	0, 0, 0,/* 08 - 0a */
342 	int bit, byte, unit;  in power5_marked_instr_event()  local
350 	bit = -1;  in power5_marked_instr_event()
357 			bit = pmc - 1;  in power5_marked_instr_event()
359 			bit = 4 - pmc;  in power5_marked_instr_event()
360 		else if (psel == 0x1b && (pmc == 1 || pmc == 3))  in power5_marked_instr_event()
368 	byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;  in power5_marked_instr_event()
371 		/* byte 1 bits 0-7, byte 2 bits 0,2-4,6 */  in power5_marked_instr_event()
373 	} else if (unit == PM_LSU1 && byte >= 4) {  in power5_marked_instr_event()
374 		byte -= 4;  in power5_marked_instr_event()
375 		/* byte 4 bits 1,3,5,7, byte 5 bits 6-7, byte 7 bits 0-4,6 */  in power5_marked_instr_event()
380 	return (mask >> (byte * 8 + bit)) & 1;  in power5_marked_instr_event()
390 	unsigned int pmc, unit, byte, psel;  in power5_compute_mmcr()  local
400 		return -1;  in power5_compute_mmcr()
410 				return -1;  in power5_compute_mmcr()
411 			if (pmc_inuse & (1 << (pmc - 1)))  in power5_compute_mmcr()
412 				return -1;  in power5_compute_mmcr()
413 			pmc_inuse |= 1 << (pmc - 1);  in power5_compute_mmcr()
414 			/* count 1/2 vs 3/4 use */  in power5_compute_mmcr()
416 				++pmc_grp_use[(pmc - 1) >> 1];  in power5_compute_mmcr()
420 			byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK;  in power5_compute_mmcr()
422 				return -1;  in power5_compute_mmcr()
425 			if (byte >= 4) {  in power5_compute_mmcr()
427 					return -1;  in power5_compute_mmcr()
429 				byte &= 3;  in power5_compute_mmcr()
432 				++pmc_grp_use[byte & 1];  in power5_compute_mmcr()
433 			if (busbyte[byte] && busbyte[byte] != unit)  in power5_compute_mmcr()
434 				return -1;  in power5_compute_mmcr()
435 			busbyte[byte] = unit;  in power5_compute_mmcr()
440 		return -1;  in power5_compute_mmcr()
459 			return -1;  in power5_compute_mmcr()
467 			return -1;  in power5_compute_mmcr()
468 		mmcr1 |= (unsigned long)(i & 3) << MMCR1_TTM1SEL_SH;  in power5_compute_mmcr()
471 		return -1;  in power5_compute_mmcr()
473 	/* Set byte lane select fields, TTM[23]SEL and GRS_*SEL. */  in power5_compute_mmcr()
474 	for (byte = 0; byte < 4; ++byte) {  in power5_compute_mmcr()
475 		unit = busbyte[byte];  in power5_compute_mmcr()
482 			/* select lower word of LSU1 for this byte */  in power5_compute_mmcr()
483 			mmcr1 |= 1ul << (MMCR1_TTM3SEL_SH + 3 - byte);  in power5_compute_mmcr()
487 			<< (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte);  in power5_compute_mmcr()
494 		byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK;  in power5_compute_mmcr()
498 			/* Bus event or any-PMC direct event */  in power5_compute_mmcr()
504 					if (grp == (byte & 1))  in power5_compute_mmcr()
514 			--pmc;  in power5_compute_mmcr()
515 			if ((psel == 8 || psel == 0x10) && isbus && (byte & 2))  in power5_compute_mmcr()
516 				/* add events on higher-numbered bus */  in power5_compute_mmcr()
517 				mmcr1 |= 1ul << (MMCR1_PMC1_ADDER_SEL_SH - pmc);  in power5_compute_mmcr()
520 			--pmc;  in power5_compute_mmcr()
529 		if (pmc <= 3)  in power5_compute_mmcr()
535 	mmcr->mmcr0 = 0;  in power5_compute_mmcr()
537 		mmcr->mmcr0 = MMCR0_PMC1CE;  in power5_compute_mmcr()
539 		mmcr->mmcr0 |= MMCR0_PMCjCE;  in power5_compute_mmcr()
540 	mmcr->mmcr1 = mmcr1;  in power5_compute_mmcr()
541 	mmcr->mmcra = mmcra;  in power5_compute_mmcr()
547 	if (pmc <= 3)  in power5_disable_pmc()
548 		mmcr->mmcr1 &= ~(0x7fUL << MMCR1_PMCSEL_SH(pmc));  in power5_disable_pmc()
563  * Table of generalized cache-related events.
564  * 0 means not supported, -1 means nonsensical, other values
575 		[C(OP_WRITE)] = {	-1,		-1		},
585 		[C(OP_WRITE)] = {	-1,		-1		},
586 		[C(OP_PREFETCH)] = {	-1,		-1		},
590 		[C(OP_WRITE)] = {	-1,		-1		},
591 		[C(OP_PREFETCH)] = {	-1,		-1		},
595 		[C(OP_WRITE)] = {	-1,		-1		},
596 		[C(OP_PREFETCH)] = {	-1,		-1		},
599 		[C(OP_READ)] = {	-1,		-1		},
600 		[C(OP_WRITE)] = {	-1,		-1		},
601 		[C(OP_PREFETCH)] = {	-1,		-1		},
626 		return -ENODEV;  in init_power5_pmu()