Lines Matching +full:1 +full:c
39 * MMCR1[25] = pmc1combine[1]
41 * MMCR1[27] = pmc2combine[1]
43 * MMCR1[29] = pmc3combine[1]
45 * MMCR1[31] = pmc4combine[1]
61 * MMCR1[17] = cache_sel[1]
65 * MMCRA[63] = 1 (SAMPLE_ENABLE)
72 * MMCRA[SDAR_MODE] = sdar_mode[0:1]
319 return -1; in power10_bhrb_filter_map()
332 return -1; in power10_bhrb_filter_map()
340 return -1; in power10_bhrb_filter_map()
351 #define C(x) PERF_COUNT_HW_CACHE_##x macro
355 * 0 means not supported, -1 means nonsensical, other values
358 static u64 power10_cache_events_dd1[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
359 [C(L1D)] = {
360 [C(OP_READ)] = {
361 [C(RESULT_ACCESS)] = PM_LD_REF_L1,
362 [C(RESULT_MISS)] = PM_LD_MISS_L1,
364 [C(OP_WRITE)] = {
365 [C(RESULT_ACCESS)] = 0,
366 [C(RESULT_MISS)] = PM_ST_MISS_L1,
368 [C(OP_PREFETCH)] = {
369 [C(RESULT_ACCESS)] = PM_LD_PREFETCH_CACHE_LINE_MISS,
370 [C(RESULT_MISS)] = 0,
373 [C(L1I)] = {
374 [C(OP_READ)] = {
375 [C(RESULT_ACCESS)] = PM_INST_FROM_L1,
376 [C(RESULT_MISS)] = PM_L1_ICACHE_MISS,
378 [C(OP_WRITE)] = {
379 [C(RESULT_ACCESS)] = PM_INST_FROM_L1MISS,
380 [C(RESULT_MISS)] = -1,
382 [C(OP_PREFETCH)] = {
383 [C(RESULT_ACCESS)] = PM_IC_PREF_REQ,
384 [C(RESULT_MISS)] = 0,
387 [C(LL)] = {
388 [C(OP_READ)] = {
389 [C(RESULT_ACCESS)] = PM_DATA_FROM_L3,
390 [C(RESULT_MISS)] = PM_DATA_FROM_L3MISS,
392 [C(OP_WRITE)] = {
393 [C(RESULT_ACCESS)] = -1,
394 [C(RESULT_MISS)] = -1,
396 [C(OP_PREFETCH)] = {
397 [C(RESULT_ACCESS)] = -1,
398 [C(RESULT_MISS)] = 0,
401 [C(DTLB)] = {
402 [C(OP_READ)] = {
403 [C(RESULT_ACCESS)] = 0,
404 [C(RESULT_MISS)] = PM_DTLB_MISS,
406 [C(OP_WRITE)] = {
407 [C(RESULT_ACCESS)] = -1,
408 [C(RESULT_MISS)] = -1,
410 [C(OP_PREFETCH)] = {
411 [C(RESULT_ACCESS)] = -1,
412 [C(RESULT_MISS)] = -1,
415 [C(ITLB)] = {
416 [C(OP_READ)] = {
417 [C(RESULT_ACCESS)] = 0,
418 [C(RESULT_MISS)] = PM_ITLB_MISS,
420 [C(OP_WRITE)] = {
421 [C(RESULT_ACCESS)] = -1,
422 [C(RESULT_MISS)] = -1,
424 [C(OP_PREFETCH)] = {
425 [C(RESULT_ACCESS)] = -1,
426 [C(RESULT_MISS)] = -1,
429 [C(BPU)] = {
430 [C(OP_READ)] = {
431 [C(RESULT_ACCESS)] = PM_BR_CMPL,
432 [C(RESULT_MISS)] = PM_BR_MPRED_CMPL,
434 [C(OP_WRITE)] = {
435 [C(RESULT_ACCESS)] = -1,
436 [C(RESULT_MISS)] = -1,
438 [C(OP_PREFETCH)] = {
439 [C(RESULT_ACCESS)] = -1,
440 [C(RESULT_MISS)] = -1,
443 [C(NODE)] = {
444 [C(OP_READ)] = {
445 [C(RESULT_ACCESS)] = -1,
446 [C(RESULT_MISS)] = -1,
448 [C(OP_WRITE)] = {
449 [C(RESULT_ACCESS)] = -1,
450 [C(RESULT_MISS)] = -1,
452 [C(OP_PREFETCH)] = {
453 [C(RESULT_ACCESS)] = -1,
454 [C(RESULT_MISS)] = -1,
459 static u64 power10_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
460 [C(L1D)] = {
461 [C(OP_READ)] = {
462 [C(RESULT_ACCESS)] = PM_LD_REF_L1,
463 [C(RESULT_MISS)] = PM_LD_MISS_L1,
465 [C(OP_WRITE)] = {
466 [C(RESULT_ACCESS)] = 0,
467 [C(RESULT_MISS)] = PM_ST_MISS_L1,
469 [C(OP_PREFETCH)] = {
470 [C(RESULT_ACCESS)] = PM_LD_PREFETCH_CACHE_LINE_MISS,
471 [C(RESULT_MISS)] = 0,
474 [C(L1I)] = {
475 [C(OP_READ)] = {
476 [C(RESULT_ACCESS)] = PM_INST_FROM_L1,
477 [C(RESULT_MISS)] = PM_L1_ICACHE_MISS,
479 [C(OP_WRITE)] = {
480 [C(RESULT_ACCESS)] = PM_INST_FROM_L1MISS,
481 [C(RESULT_MISS)] = -1,
483 [C(OP_PREFETCH)] = {
484 [C(RESULT_ACCESS)] = PM_IC_PREF_REQ,
485 [C(RESULT_MISS)] = 0,
488 [C(LL)] = {
489 [C(OP_READ)] = {
490 [C(RESULT_ACCESS)] = PM_DATA_FROM_L3,
491 [C(RESULT_MISS)] = PM_DATA_FROM_L3MISS,
493 [C(OP_WRITE)] = {
494 [C(RESULT_ACCESS)] = PM_L2_ST,
495 [C(RESULT_MISS)] = PM_L2_ST_MISS,
497 [C(OP_PREFETCH)] = {
498 [C(RESULT_ACCESS)] = PM_L3_PF_MISS_L3,
499 [C(RESULT_MISS)] = 0,
502 [C(DTLB)] = {
503 [C(OP_READ)] = {
504 [C(RESULT_ACCESS)] = 0,
505 [C(RESULT_MISS)] = PM_DTLB_MISS,
507 [C(OP_WRITE)] = {
508 [C(RESULT_ACCESS)] = -1,
509 [C(RESULT_MISS)] = -1,
511 [C(OP_PREFETCH)] = {
512 [C(RESULT_ACCESS)] = -1,
513 [C(RESULT_MISS)] = -1,
516 [C(ITLB)] = {
517 [C(OP_READ)] = {
518 [C(RESULT_ACCESS)] = 0,
519 [C(RESULT_MISS)] = PM_ITLB_MISS,
521 [C(OP_WRITE)] = {
522 [C(RESULT_ACCESS)] = -1,
523 [C(RESULT_MISS)] = -1,
525 [C(OP_PREFETCH)] = {
526 [C(RESULT_ACCESS)] = -1,
527 [C(RESULT_MISS)] = -1,
530 [C(BPU)] = {
531 [C(OP_READ)] = {
532 [C(RESULT_ACCESS)] = PM_BR_CMPL,
533 [C(RESULT_MISS)] = PM_BR_MPRED_CMPL,
535 [C(OP_WRITE)] = {
536 [C(RESULT_ACCESS)] = -1,
537 [C(RESULT_MISS)] = -1,
539 [C(OP_PREFETCH)] = {
540 [C(RESULT_ACCESS)] = -1,
541 [C(RESULT_MISS)] = -1,
544 [C(NODE)] = {
545 [C(OP_READ)] = {
546 [C(RESULT_ACCESS)] = -1,
547 [C(RESULT_MISS)] = -1,
549 [C(OP_WRITE)] = {
550 [C(RESULT_ACCESS)] = -1,
551 [C(RESULT_MISS)] = -1,
553 [C(OP_PREFETCH)] = {
554 [C(RESULT_ACCESS)] = -1,
555 [C(RESULT_MISS)] = -1,
560 #undef C
617 if ((PVR_CFG(pvr) == 1)) in init_power10_pmu()
623 if ((PVR_CFG(pvr) == 1)) { in init_power10_pmu()