Lines Matching +full:1 +full:- +full:v0
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 /* 0 == don't use VMX, 1 == use VMX */
26 std r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
40 clrldi r6,r6,(64-3)
42 bf cr7*4+3,1f
44 addi r4,r4,1
46 addi r3,r3,1
48 1: bf cr7*4+2,2f
54 2: bf cr7*4+1,3f
65 stdu r1,-STACKFRAMESIZE(r1)
119 clrldi r5,r5,(64-7)
136 6: bf cr7*4+1,7f
178 9: clrldi r5,r5,(64-4)
191 12: bf cr7*4+1,13f
207 15: ld r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
217 std r4,-STACKFRAMESIZE+STK_REG(R30)(r1)
218 std r5,-STACKFRAMESIZE+STK_REG(R29)(r1)
220 stdu r1,-STACKFRAMESIZE(r1)
232 * 1 for the store side.
236 ori r9,r9,1 /* stream=1 */
240 ble 1f
242 1: lis r0,0x0E00 /* depth=7 */
245 ori r10,r7,1 /* stream=1 */
256 rldicl. r6,r6,0,(64-4)
262 clrldi r6,r6,(64-4)
264 bf cr7*4+3,1f
266 addi r4,r4,1
268 addi r3,r3,1
270 1: bf cr7*4+2,2f
276 2: bf cr7*4+1,3f
294 clrldi r6,r6,(64-7)
308 lvx v0,r4,r9
311 stvx v0,r3,r9
314 6: bf cr7*4+1,7f
318 lvx v0,r4,r11
323 stvx v0,r3,r11
353 lvx v0,r4,r16
362 stvx v0,r3,r16
371 clrldi r5,r5,(64-7)
375 bf cr7*4+1,9f
379 lvx v0,r4,r11
384 stvx v0,r3,r11
389 lvx v0,r4,r9
392 stvx v0,r3,r9
402 11: clrldi r5,r5,(64-4)
410 12: bf cr7*4+1,13f
427 ld r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
434 clrldi r6,r6,(64-4)
436 bf cr7*4+3,1f
438 addi r4,r4,1
440 addi r3,r3,1
442 1: bf cr7*4+2,2f
448 2: bf cr7*4+1,3f
468 clrldi r6,r6,(64-7)
475 lvx v0,0,r4
480 VPERM(v8,v0,v1,v16)
484 vor v0,v1,v1
488 VPERM(v8,v0,v1,v16)
489 lvx v0,r4,r9
490 VPERM(v9,v1,v0,v16)
496 6: bf cr7*4+1,7f
498 VPERM(v8,v0,v3,v16)
503 lvx v0,r4,r11
504 VPERM(v11,v1,v0,v16)
533 VPERM(v8,v0,v7,v16)
546 lvx v0,r4,r16
547 VPERM(v15,v1,v0,v16)
565 clrldi r5,r5,(64-7)
569 bf cr7*4+1,9f
571 VPERM(v8,v0,v3,v16)
576 lvx v0,r4,r11
577 VPERM(v11,v1,v0,v16)
587 VPERM(v8,v0,v1,v16)
588 lvx v0,r4,r9
589 VPERM(v9,v1,v0,v16)
597 VPERM(v8,v0,v1,v16)
603 11: clrldi r5,r5,(64-4)
604 addi r4,r4,-16 /* Unwind the +16 load offset */
614 12: bf cr7*4+1,13f
631 ld r3,-STACKFRAMESIZE+STK_REG(R31)(r1)