Lines Matching +full:bl +full:- +full:name
1 /* SPDX-License-Identifier: GPL-2.0 */
7 #include <asm/asm-offsets.h>
12 #include <asm/asm-compat.h>
47 * Note that on 32-bit this can only use registers that will be
48 * restored by fast_exception_return, i.e. r3 - r6, r10 and r11.
69 li r4,-1
119 #error This asm code isn't ready for 32-bit kernels
158 * usage of floating-point registers. These routines must be called
166 .long 0x3f800000 /* 1.0 in single-precision FP */
168 .long 0x3f000000 /* 0.5 in single-precision FP */
170 #define LDCONST(fr, name) \ argument
171 lis r11,name@ha; \
172 lfs fr,name@l(r11)
183 #define LDCONST(fr, name) \ argument
184 pla r11,name@pcrel; \
187 #define LDCONST(fr, name) \ argument
188 addis r11,r2,name@toc@ha; \
189 lfd fr,name@toc@l(r11)
199 stwu r1,-64(r1)
201 stdu r1,-64(r1)
232 bl fpenable
249 bl fpenable
266 bl fpenable
286 bl fpenable
303 * r3 -> destination, r4 -> source.
307 bl fpenable
320 * Vector reciprocal square-root estimate, floating point.
322 * by 2 iterations of Newton-Raphson to get sufficient accuracy.
323 * r3 -> destination, r4 -> source.
327 bl fpenable
341 fnmsubs fr3,fr1,fr3,fr4 /* 1 - s * r * r */
342 fmadds fr1,fr2,fr3,fr1 /* r = r + 0.5 * r * (1 - s * r * r) */
345 fnmsubs fr3,fr1,fr3,fr4 /* 1 - s * r * r */
346 fmadds fr1,fr2,fr3,fr1 /* r = r + 0.5 * r * (1 - s * r * r) */