Lines Matching +full:turn +full:- +full:off
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 Copyright © 1997-1998 by PowerLogix R & D, Inc.
9 - First public release, contributed by PowerLogix.
12 - Terry: Made sure code disabled interrupts before running. (Previously
14 - Terry: Updated for tentative G4 support. 4MB of memory is now flushed
16 - Terry: Updated for workaround to HID0[DPM] processor bug
20 - Terry: Added isync to correct for an errata.
23 - DanM: Finally added the 7450 patch I've had for the past
29 Please e-mail updates to this file to me, thanks!
36 #include <asm/feature-fixups.h>
54 _setL2CR(0) - disables the cache
55 _setL2CR(0xB3A04000) - enables my G3 upgrade card:
56 - L2E set to turn on the cache
57 - L2SIZ set to 1MB
58 - L2CLK set to 1:1
59 - L2RAM set to pipelined synchronous late-write
60 - L2I set to perform a global invalidation
61 - L2OH set to 0.5 nS
62 - L2DF set because this upgrade card
76 The size is read-only for these processors with internal L2
78 -- Dan
86 * -- paulus.
91 li r3,-1
103 /* Turn off interrupts and data relocation. */
106 rlwinm r4,r4,0,28,26 /* Turn off DR bit */
117 rlwinm r4,r8,0,12,10 /* Turn off HID0[DPM] */
127 rlwinm r3,r3,0,11,9 /* Turn off the invalidate bit */
128 rlwinm r3,r3,0,1,31 /* Turn off the enable bit */
140 /**** Might be a good idea to set L2DO here - to prevent instructions
189 /* Set up the L2CR configuration bits (and switch L2 off) */
228 11: rlwinm r3,r3,0,11,9 /* Turn off the L2I bit */
282 li r3,-1
286 /* Turn off interrupts and data relocation. */
289 rlwinm r4,r4,0,28,26 /* Turn off DR bit */
303 rlwinm r3,r3,0,22,20 /* Turn off the invalidate bit */
304 rlwinm r3,r3,0,2,31 /* Turn off the enable & PE bits */
305 rlwinm r3,r3,0,5,3 /* Turn off the clken bit */
325 /* Set up the L3CR configuration bits (and switch L3 off) */
355 rlwinm r3,r3,0,5,3 /* Turn off the clken bit */
392 /* --- End of PowerLogix code ---
396 /* flush_disable_L1() - Flush and disable L1 cache
439 /* inval_enable_L1 - Invalidate and enable L1 cache
441 * Assumes L1 is already disabled and MSR:EE is off