Lines Matching refs:r10
305 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
311 mfspr r10, SPRN_DEAR /* Get faulting address */
317 cmplw cr7, r10, r11
363 rlwinm r12, r10, PPC44x_PGD_OFF_SHIFT, PPC44x_PGD_OFF_MASK_BIT, 29
369 rlwimi r12, r10, PPC44x_PTE_ADD_SHIFT, PPC44x_PTE_ADD_MASK_BIT, 28
373 lis r10,tlb_44x_index@ha
378 lwz r13,tlb_44x_index@l(r10)
392 stw r13,tlb_44x_index@l(r10)
395 mfspr r10,SPRN_DEAR
409 mfspr r10, SPRN_SPRG_RSCRATCH0
419 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
425 mfspr r10, SPRN_SRR0 /* Get faulting address */
431 cmplw cr7, r10, r11
462 rlwinm r12, r10, PPC44x_PGD_OFF_SHIFT, PPC44x_PGD_OFF_MASK_BIT, 29
468 rlwimi r12, r10, PPC44x_PTE_ADD_SHIFT, PPC44x_PTE_ADD_MASK_BIT, 28
472 lis r10,tlb_44x_index@ha
477 lwz r13,tlb_44x_index@l(r10)
491 stw r13,tlb_44x_index@l(r10)
494 mfspr r10,SPRN_SRR0
508 mfspr r10, SPRN_SPRG_RSCRATCH0
533 rlwimi r10,r11,0,PPC44x_PTE_ADD_MASK_BIT,31
534 tlbwe r10,r13,PPC44x_TLB_PAGEID /* Write PAGEID */
537 li r10,0xf84 /* Mask to apply from PTE */
538 rlwimi r10,r12,29,30,31 /* DIRTY,READ -> SW,SR position */
539 and r11,r12,r10 /* Mask PTE bits to keep */
552 mfspr r10, SPRN_SPRG_RSCRATCH0
559 mtspr SPRN_SPRG_WSCRATCH0,r10 /* Save some working registers */
565 mfspr r10,SPRN_DEAR /* Get faulting address */
571 cmplw cr7,r10,r11
607 rlwinm r12,r10,PPC44x_PGD_OFF_SHIFT,PPC44x_PGD_OFF_MASK_BIT,29
612 rlwimi r10,r12,0,32-PAGE_SHIFT,31 /* Insert valid and page size*/
614 tlbwe r10,r12,0
624 rlwimi r12,r10,PPC44x_PTE_ADD_SHIFT,PPC44x_PTE_ADD_MASK_BIT,28
650 mfspr r10,SPRN_SPRG_RSCRATCH0
660 mtspr SPRN_SPRG_WSCRATCH0,r10 /* Save some working registers */
666 mfspr r10,SPRN_SRR0 /* Get faulting address */
672 cmplw cr7,r10,r11
694 rlwinm r12,r10,PPC44x_PGD_OFF_SHIFT,PPC44x_PGD_OFF_MASK_BIT,29
699 rlwimi r10,r12,0,32-PAGE_SHIFT,31 /* Insert valid and page size*/
701 tlbwe r10,r12,0
711 rlwimi r12,r10,PPC44x_PTE_ADD_SHIFT,PPC44x_PTE_ADD_MASK_BIT,28
737 mfspr r10, SPRN_SPRG_RSCRATCH0
757 li r10,0xf84 /* Mask to apply from PTE */
758 rlwimi r10,r12,29,30,31 /* DIRTY,READ -> SW,SR position */
759 and r11,r12,r10 /* Mask PTE bits to keep */
772 mfspr r10, SPRN_SPRG_RSCRATCH0