Lines Matching +full:0 +full:xf20
130 IHSRR=0
133 IHSRR_IF_HVMODE=0
142 IISIDE=0
148 ICFAR_IF_HVMODE=0
151 IDAR=0
154 IDSISR=0
160 IREALMODE_COMMON=0
163 .error "IREALMODE_COMMON=1 but IBRANCH_TO_COMMON=0"
167 IMASK=0
170 IKVM_REAL=0
173 IKVM_VIRT=0
182 IMSR_R12=0
192 * taken with MSR[HV]=0.
201 * runs with MSR[HV]=0, so the host takes all interrupts on behalf of the
202 * guest. PR KVM runs with LPCR[AIL]=0 which causes interrupts to always be
206 * Interrupts that are taken in MSR[HV]=0 and escalate to MSR[HV]=1 are always
221 cmpwi r10,0
222 /* HSRR variants have the 0x2 bit added to their trap number */
225 li r10,(IVEC + 0x2)
230 li r10,(IVEC + 0x2)
281 .macro GEN_INT_ENTRY name, virt, ool=0
301 li r10,0
456 cmpdi r12,0
467 .if IVEC == 0x500 || IVEC == 0xea0
469 .elseif IVEC == 0x900
471 .elseif IVEC == 0xa00 || IVEC == 0xe80
473 .elseif IVEC == 0xe60
475 .elseif IVEC == 0xf00
501 EMIT_BUG_ENTRY 100b,__FILE__,__LINE__,0
507 std r10,0(r1) /* make stack chain pointer */
510 SANITIZE_GPR(0)
586 li r10,0
603 li r10,0
614 * If stack=0, then the stack is already set in r1, and r1 is saved in r10.
636 ld r12,0(r9)
648 li r12,0
666 ld r12,0(r9)
678 li r12,0
686 .macro EXCEPTION_RESTORE_REGS hsrr=0
689 li r10,0
713 REST_GPR(0, r1)
742 tdi 0,0,0x48 // Trap never, or in reverse endian: b . + 8
744 .long 0xa643707d // mtsprg 0, r11 Backup r11
745 .long 0xa6027a7d // mfsrr0 r11
746 .long 0xa643727d // mtsprg 2, r11 Backup SRR0 in SPRG2
747 .long 0xa6027b7d // mfsrr1 r11
748 .long 0xa643737d // mtsprg 3, r11 Backup SRR1 in SPRG3
749 .long 0xa600607d // mfmsr r11
750 .long 0x01006b69 // xori r11, r11, 1 Invert MSR[LE]
751 .long 0xa6037b7d // mtsrr1 r11
756 .long 0x00006039 | \
757 ((ABS_ADDR(1f, real_vectors) & 0x00ff) << 24) | \
758 ((ABS_ADDR(1f, real_vectors) & 0xff00) << 8)
759 .long 0xa6037a7d // mtsrr0 r11
760 .long 0x2400004c // rfid
766 mfsprg r11, 0 // Restore r11
774 mtsprg 0, r11
776 cmpdi r13, 0
779 mfsprg r11, 0
780 END_FTR_SECTION(0, 1) // nop out after boot
786 * - Virtual mode exceptions must be mapped at their 0xc000... location.
790 * - LOAD_HANDLER targets must be within first 64K of physical 0 /
791 * virtual 0xc00...
801 * are offset by 0xc000000000000000 and also tend to get an added 0x4000
807 * The scv instructions are a special case. They get a 0x3000 offset applied.
810 * It's impossible to receive interrupts below 0x300 via AIL.
813 * escalated to HV=1 from HV=0 is delivered via real mode handlers.
817 * 0x0000 - 0x00ff : Secondary processor spin code
818 * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors
819 * 0x1900 - 0x2fff : Real mode trampolines
820 * 0x3000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors
821 * 0x5900 - 0x6fff : Relon mode trampolines
822 * 0x7000 - 0x7fff : FWNMI data area
823 * 0x8000 - .... : Common interrupt handlers, remaining early
826 * We could reclaim 0x4000-0x42ff for real mode trampolines if the space
830 OPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900)
831 OPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x3000)
832 OPEN_FIXED_SECTION(virt_vectors, 0x3000, 0x5900)
833 OPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000)
845 * This address (0x7000) is fixed by the RPA.
847 * 0x7000 to 0x8000 free for use by the firmware
849 ZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000)
850 OPEN_TEXT_SECTION(0x8000)
852 OPEN_TEXT_SECTION(0x7000)
861 * address 0x100 when we are running a relocatable kernel.
869 * Interrupt 0x3000 - System Call Vectored Interrupt (syscall).
880 * AIL-0 mode scv exceptions go to 0x17000-0x17fff, but we set AIL-3 and
881 * ensure scv is never executed with relocation off, which means AIL-0
891 * These interrupts do not elevate HV 0->1, so HV is not involved. PR KVM
898 EXC_VIRT_BEGIN(system_call_vectored, 0x3000, 0x1000)
899 /* SCV 0 */
928 EXC_VIRT_END(system_call_vectored, 0x3000, 0x1000)
933 SOFT_MASK_TABLE(0xc000000000003000, 0xc000000000004000)
948 /* No virt vectors corresponding with 0x0..0x100 */
949 EXC_VIRT_NONE(0x4000, 0x100)
953 * Interrupt 0x100 - System Reset Interrupt (SRESET aka NMI).
978 * send the sreset to 0x100 in the guest if it is not fwnmi capable.
986 IVEC=0x100
988 IVIRT=0 /* no virt entry point */
989 ISTACK=0
993 EXC_REAL_BEGIN(system_reset, 0x100, 0x100)
998 * bits 46:47. A non-0 value indicates that we are coming from a power
1000 * but we branch to the 0xc000... address so we can turn on relocation
1014 std r3,PACA_EXNMI+0*8(r13)
1018 mfocrf r4,0x80
1022 mtocrf 0x80,r4
1023 ld r3,PACA_EXNMI+0*8(r13)
1030 GEN_INT_ENTRY system_reset, virt=0
1038 EXC_REAL_END(system_reset, 0x100, 0x100)
1039 EXC_VIRT_NONE(0x4100, 0x100)
1056 GEN_INT_ENTRY system_reset, virt=0
1081 li r9,0
1097 * Interrupt 0x200 - Machine Check Interrupt (MCE).
1140 IVEC=0x200
1142 IVIRT=0 /* no virt entry point */
1144 ISTACK=0
1147 IKUAP=0 /* We don't touch AMR here, we never go to virtual mode */
1151 IVEC=0x200
1153 IVIRT=0 /* no virt entry point */
1159 EXC_REAL_BEGIN(machine_check, 0x200, 0x100)
1161 GEN_INT_ENTRY machine_check_early, virt=0
1162 EXC_REAL_END(machine_check, 0x200, 0x100)
1163 EXC_VIRT_NONE(0x4200, 0x100)
1168 GEN_INT_ENTRY machine_check_early, virt=0
1173 li r9,0; \
1197 * NOTE: We are here with MSR_ME=0 (off), which means we risk a
1206 cmpwi r10,0 /* Are we in nested machine check */
1227 END_FTR_SECTION(0, 1) // nop out after boot
1256 cmpwi r11,0 /* Check if coming from guest */
1281 cmpdi r3,0 /* see if we handled MCE successfully */
1306 GEN_INT_ENTRY machine_check, virt=0
1362 li r10,0 /* clear MSR_RI */
1393 * Interrupt 0x300 - Data Storage Interrupt (DSI).
1423 IVEC=0x300
1429 EXC_REAL_BEGIN(data_access, 0x300, 0x80)
1430 GEN_INT_ENTRY data_access, virt=0
1431 EXC_REAL_END(data_access, 0x300, 0x80)
1432 EXC_VIRT_BEGIN(data_access, 0x4300, 0x80)
1434 EXC_VIRT_END(data_access, 0x4300, 0x80)
1462 * Interrupt 0x380 - Data Segment Interrupt (DSLB).
1476 * KVM: Same as 0x300, DSLB must test for KVM guest.
1479 IVEC=0x380
1484 EXC_REAL_BEGIN(data_access_slb, 0x380, 0x80)
1485 GEN_INT_ENTRY data_access_slb, virt=0
1486 EXC_REAL_END(data_access_slb, 0x380, 0x80)
1487 EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80)
1489 EXC_VIRT_END(data_access_slb, 0x4380, 0x80)
1497 cmpdi r3,0
1515 * Interrupt 0x400 - Instruction Storage Interrupt (ISI).
1524 IVEC=0x400
1533 EXC_REAL_BEGIN(instruction_access, 0x400, 0x80)
1534 GEN_INT_ENTRY instruction_access, virt=0
1535 EXC_REAL_END(instruction_access, 0x400, 0x80)
1536 EXC_VIRT_BEGIN(instruction_access, 0x4400, 0x80)
1538 EXC_VIRT_END(instruction_access, 0x4400, 0x80)
1555 * Interrupt 0x480 - Instruction Segment Interrupt (ISLB).
1564 IVEC=0x480
1572 EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x80)
1573 GEN_INT_ENTRY instruction_access_slb, virt=0
1574 EXC_REAL_END(instruction_access_slb, 0x480, 0x80)
1575 EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x80)
1577 EXC_VIRT_END(instruction_access_slb, 0x4480, 0x80)
1585 cmpdi r3,0
1603 * Interrupt 0x500 - External Interrupt.
1632 IVEC=0x500
1637 ICFAR=0
1643 EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x100)
1644 GEN_INT_ENTRY hardware_interrupt, virt=0
1645 EXC_REAL_END(hardware_interrupt, 0x500, 0x100)
1646 EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x100)
1648 EXC_VIRT_END(hardware_interrupt, 0x4500, 0x100)
1661 * Interrupt 0x600 - Alignment Interrupt
1665 IVEC=0x600
1673 EXC_REAL_BEGIN(alignment, 0x600, 0x100)
1674 GEN_INT_ENTRY alignment, virt=0
1675 EXC_REAL_END(alignment, 0x600, 0x100)
1676 EXC_VIRT_BEGIN(alignment, 0x4600, 0x100)
1678 EXC_VIRT_END(alignment, 0x4600, 0x100)
1688 * Interrupt 0x700 - Program Interrupt (program check).
1697 IVEC=0x700
1703 EXC_REAL_BEGIN(program_check, 0x700, 0x100)
1705 GEN_INT_ENTRY program_check, virt=0
1706 EXC_REAL_END(program_check, 0x700, 0x100)
1707 EXC_VIRT_BEGIN(program_check, 0x4700, 0x100)
1709 EXC_VIRT_END(program_check, 0x4700, 0x100)
1738 __ISTACK(program_check)=0
1754 * Interrupt 0x800 - Floating-Point Unavailable Interrupt.
1756 * with MSR[FP]=0.
1763 IVEC=0x800
1770 EXC_REAL_BEGIN(fp_unavailable, 0x800, 0x100)
1771 GEN_INT_ENTRY fp_unavailable, virt=0
1772 EXC_REAL_END(fp_unavailable, 0x800, 0x100)
1773 EXC_VIRT_BEGIN(fp_unavailable, 0x4800, 0x100)
1775 EXC_VIRT_END(fp_unavailable, 0x4800, 0x100)
1781 0: trap
1782 EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0
1804 * Interrupt 0x900 - Decrementer Interrupt.
1811 * This calls into Linux timer handler. NVGPRs are not saved (see 0x500).
1825 IVEC=0x900
1830 ICFAR=0
1833 EXC_REAL_BEGIN(decrementer, 0x900, 0x80)
1834 GEN_INT_ENTRY decrementer, virt=0
1835 EXC_REAL_END(decrementer, 0x900, 0x80)
1836 EXC_VIRT_BEGIN(decrementer, 0x4900, 0x80)
1838 EXC_VIRT_END(decrementer, 0x4900, 0x80)
1847 * Interrupt 0x980 - Hypervisor Decrementer Interrupt.
1848 * This is an asynchronous interrupt, similar to 0x900 but for the HDEC
1857 IVEC=0x980
1859 ISTACK=0
1864 EXC_REAL_BEGIN(hdecrementer, 0x980, 0x80)
1865 GEN_INT_ENTRY hdecrementer, virt=0
1866 EXC_REAL_END(hdecrementer, 0x980, 0x80)
1867 EXC_VIRT_BEGIN(hdecrementer, 0x4980, 0x80)
1869 EXC_VIRT_END(hdecrementer, 0x4980, 0x80)
1880 li r10,0
1884 mtcrf 0x80,r9
1894 * Interrupt 0xa00 - Directed Privileged Doorbell Interrupt.
1901 * hypervisor supports it. NVGPRS are not saved (see 0x500).
1910 IVEC=0xa00
1915 ICFAR=0
1918 EXC_REAL_BEGIN(doorbell_super, 0xa00, 0x100)
1919 GEN_INT_ENTRY doorbell_super, virt=0
1920 EXC_REAL_END(doorbell_super, 0xa00, 0x100)
1921 EXC_VIRT_BEGIN(doorbell_super, 0x4a00, 0x100)
1923 EXC_VIRT_END(doorbell_super, 0x4a00, 0x100)
1935 EXC_REAL_NONE(0xb00, 0x100)
1936 EXC_VIRT_NONE(0x4b00, 0x100)
1939 * Interrupt 0xc00 - System Call Interrupt (syscall, hcall).
1941 * system call is invoked with "sc 0" and does not alter the HV bit, so it
1945 * In HPT, sc 1 always goes to 0xc00 real mode. In RADIX, sc 1 can go to
1946 * 0x4c00 virtual mode.
1964 IVEC=0xc00
1967 ICFAR=0
2013 EXC_REAL_BEGIN(system_call, 0xc00, 0x100)
2014 SYSTEM_CALL 0
2015 EXC_REAL_END(system_call, 0xc00, 0x100)
2016 EXC_VIRT_BEGIN(system_call, 0x4c00, 0x100)
2018 EXC_VIRT_END(system_call, 0x4c00, 0x100)
2028 li r10,0
2057 * Interrupt 0xd00 - Trace Interrupt.
2062 IVEC=0xd00
2068 EXC_REAL_BEGIN(single_step, 0xd00, 0x100)
2069 GEN_INT_ENTRY single_step, virt=0
2070 EXC_REAL_END(single_step, 0xd00, 0x100)
2071 EXC_VIRT_BEGIN(single_step, 0x4d00, 0x100)
2073 EXC_VIRT_END(single_step, 0x4d00, 0x100)
2082 * Interrupt 0xe00 - Hypervisor Data Storage Interrupt (HDSI).
2094 IVEC=0xe00
2102 EXC_REAL_BEGIN(h_data_storage, 0xe00, 0x20)
2103 GEN_INT_ENTRY h_data_storage, virt=0, ool=1
2104 EXC_REAL_END(h_data_storage, 0xe00, 0x20)
2105 EXC_VIRT_BEGIN(h_data_storage, 0x4e00, 0x20)
2107 EXC_VIRT_END(h_data_storage, 0x4e00, 0x20)
2120 * Interrupt 0xe20 - Hypervisor Instruction Storage Interrupt (HISI).
2125 IVEC=0xe20
2131 EXC_REAL_BEGIN(h_instr_storage, 0xe20, 0x20)
2132 GEN_INT_ENTRY h_instr_storage, virt=0, ool=1
2133 EXC_REAL_END(h_instr_storage, 0xe20, 0x20)
2134 EXC_VIRT_BEGIN(h_instr_storage, 0x4e20, 0x20)
2136 EXC_VIRT_END(h_instr_storage, 0x4e20, 0x20)
2145 * Interrupt 0xe40 - Hypervisor Emulation Assistance Interrupt.
2148 IVEC=0xe40
2154 EXC_REAL_BEGIN(emulation_assist, 0xe40, 0x20)
2155 GEN_INT_ENTRY emulation_assist, virt=0, ool=1
2156 EXC_REAL_END(emulation_assist, 0xe40, 0x20)
2157 EXC_VIRT_BEGIN(emulation_assist, 0x4e40, 0x20)
2159 EXC_VIRT_END(emulation_assist, 0x4e40, 0x20)
2169 * Interrupt 0xe60 - Hypervisor Maintenance Interrupt (HMI).
2193 IVEC=0xe60
2196 ISTACK=0
2197 IKUAP=0 /* We don't touch AMR here, we never go to virtual mode */
2202 IVEC=0xe60
2208 EXC_REAL_BEGIN(hmi_exception, 0xe60, 0x20)
2209 GEN_INT_ENTRY hmi_exception_early, virt=0, ool=1
2210 EXC_REAL_END(hmi_exception, 0xe60, 0x20)
2211 EXC_VIRT_NONE(0x4e60, 0x20)
2224 cmpdi cr0,r3,0
2236 GEN_INT_ENTRY hmi_exception, virt=0
2246 * Interrupt 0xe80 - Directed Hypervisor Doorbell Interrupt.
2248 * Similar to the 0xa00 doorbell but for host rather than guest.
2256 IVEC=0xe80
2262 ICFAR=0
2266 EXC_REAL_BEGIN(h_doorbell, 0xe80, 0x20)
2267 GEN_INT_ENTRY h_doorbell, virt=0, ool=1
2268 EXC_REAL_END(h_doorbell, 0xe80, 0x20)
2269 EXC_VIRT_BEGIN(h_doorbell, 0x4e80, 0x20)
2271 EXC_VIRT_END(h_doorbell, 0x4e80, 0x20)
2284 * Interrupt 0xea0 - Hypervisor Virtualization Interrupt.
2286 * Similar to 0x500 but for host only.
2292 IVEC=0xea0
2298 ICFAR=0
2302 EXC_REAL_BEGIN(h_virt_irq, 0xea0, 0x20)
2303 GEN_INT_ENTRY h_virt_irq, virt=0, ool=1
2304 EXC_REAL_END(h_virt_irq, 0xea0, 0x20)
2305 EXC_VIRT_BEGIN(h_virt_irq, 0x4ea0, 0x20)
2307 EXC_VIRT_END(h_virt_irq, 0x4ea0, 0x20)
2315 EXC_REAL_NONE(0xec0, 0x20)
2316 EXC_VIRT_NONE(0x4ec0, 0x20)
2317 EXC_REAL_NONE(0xee0, 0x20)
2318 EXC_VIRT_NONE(0x4ee0, 0x20)
2322 * Interrupt 0xf00 - Performance Monitor Interrupt (PMI, PMU).
2340 IVEC=0xf00
2345 ICFAR=0
2348 EXC_REAL_BEGIN(performance_monitor, 0xf00, 0x20)
2349 GEN_INT_ENTRY performance_monitor, virt=0, ool=1
2350 EXC_REAL_END(performance_monitor, 0xf00, 0x20)
2351 EXC_VIRT_BEGIN(performance_monitor, 0x4f00, 0x20)
2353 EXC_VIRT_END(performance_monitor, 0x4f00, 0x20)
2365 li r9,0
2370 EXCEPTION_RESTORE_REGS hsrr=0
2374 * Interrupt 0xf20 - Vector Unavailable Interrupt.
2376 * executing a vector (or altivec) instruction with MSR[VEC]=0.
2380 IVEC=0xf20
2387 EXC_REAL_BEGIN(altivec_unavailable, 0xf20, 0x20)
2388 GEN_INT_ENTRY altivec_unavailable, virt=0, ool=1
2389 EXC_REAL_END(altivec_unavailable, 0xf20, 0x20)
2390 EXC_VIRT_BEGIN(altivec_unavailable, 0x4f20, 0x20)
2392 EXC_VIRT_END(altivec_unavailable, 0x4f20, 0x20)
2424 * Interrupt 0xf40 - VSX Unavailable Interrupt.
2426 * executing a VSX instruction with MSR[VSX]=0.
2430 IVEC=0xf40
2437 EXC_REAL_BEGIN(vsx_unavailable, 0xf40, 0x20)
2438 GEN_INT_ENTRY vsx_unavailable, virt=0, ool=1
2439 EXC_REAL_END(vsx_unavailable, 0xf40, 0x20)
2440 EXC_VIRT_BEGIN(vsx_unavailable, 0x4f40, 0x20)
2442 EXC_VIRT_END(vsx_unavailable, 0x4f40, 0x20)
2473 * Interrupt 0xf60 - Facility Unavailable Interrupt.
2480 IVEC=0xf60
2486 EXC_REAL_BEGIN(facility_unavailable, 0xf60, 0x20)
2487 GEN_INT_ENTRY facility_unavailable, virt=0, ool=1
2488 EXC_REAL_END(facility_unavailable, 0xf60, 0x20)
2489 EXC_VIRT_BEGIN(facility_unavailable, 0x4f60, 0x20)
2491 EXC_VIRT_END(facility_unavailable, 0x4f60, 0x20)
2501 * Interrupt 0xf60 - Hypervisor Facility Unavailable Interrupt.
2508 IVEC=0xf80
2514 EXC_REAL_BEGIN(h_facility_unavailable, 0xf80, 0x20)
2515 GEN_INT_ENTRY h_facility_unavailable, virt=0, ool=1
2516 EXC_REAL_END(h_facility_unavailable, 0xf80, 0x20)
2517 EXC_VIRT_BEGIN(h_facility_unavailable, 0x4f80, 0x20)
2519 EXC_VIRT_END(h_facility_unavailable, 0x4f80, 0x20)
2529 EXC_REAL_NONE(0xfa0, 0x20)
2530 EXC_VIRT_NONE(0x4fa0, 0x20)
2531 EXC_REAL_NONE(0xfc0, 0x20)
2532 EXC_VIRT_NONE(0x4fc0, 0x20)
2533 EXC_REAL_NONE(0xfe0, 0x20)
2534 EXC_VIRT_NONE(0x4fe0, 0x20)
2536 EXC_REAL_NONE(0x1000, 0x100)
2537 EXC_VIRT_NONE(0x5000, 0x100)
2538 EXC_REAL_NONE(0x1100, 0x100)
2539 EXC_VIRT_NONE(0x5100, 0x100)
2543 IVEC=0x1200
2547 EXC_REAL_BEGIN(cbe_system_error, 0x1200, 0x100)
2548 GEN_INT_ENTRY cbe_system_error, virt=0
2549 EXC_REAL_END(cbe_system_error, 0x1200, 0x100)
2550 EXC_VIRT_NONE(0x5200, 0x100)
2558 EXC_REAL_NONE(0x1200, 0x100)
2559 EXC_VIRT_NONE(0x5200, 0x100)
2563 * Interrupt 0x1300 - Instruction Address Breakpoint Interrupt.
2570 IVEC=0x1300
2576 EXC_REAL_BEGIN(instruction_breakpoint, 0x1300, 0x100)
2577 GEN_INT_ENTRY instruction_breakpoint, virt=0
2578 EXC_REAL_END(instruction_breakpoint, 0x1300, 0x100)
2579 EXC_VIRT_BEGIN(instruction_breakpoint, 0x5300, 0x100)
2581 EXC_VIRT_END(instruction_breakpoint, 0x5300, 0x100)
2589 EXC_REAL_NONE(0x1400, 0x100)
2590 EXC_VIRT_NONE(0x5400, 0x100)
2593 * Interrupt 0x1500 - Soft Patch Interrupt
2605 IVEC=0x1500
2607 IBRANCH_TO_COMMON=0
2611 EXC_REAL_BEGIN(denorm_exception, 0x1500, 0x100)
2612 GEN_INT_ENTRY denorm_exception, virt=0
2617 GEN_BRANCH_TO_COMMON denorm_exception, virt=0
2618 EXC_REAL_END(denorm_exception, 0x1500, 0x100)
2620 EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x100)
2625 EXC_VIRT_END(denorm_exception, 0x5500, 0x100)
2627 EXC_VIRT_NONE(0x5500, 0x100)
2643 .Lreg=0
2659 .Lreg=0
2684 mtcrf 0x80,r9
2694 li r10,0
2713 IVEC=0x1600
2717 EXC_REAL_BEGIN(cbe_maintenance, 0x1600, 0x100)
2718 GEN_INT_ENTRY cbe_maintenance, virt=0
2719 EXC_REAL_END(cbe_maintenance, 0x1600, 0x100)
2720 EXC_VIRT_NONE(0x5600, 0x100)
2728 EXC_REAL_NONE(0x1600, 0x100)
2729 EXC_VIRT_NONE(0x5600, 0x100)
2734 IVEC=0x1700
2740 EXC_REAL_BEGIN(altivec_assist, 0x1700, 0x100)
2741 GEN_INT_ENTRY altivec_assist, virt=0
2742 EXC_REAL_END(altivec_assist, 0x1700, 0x100)
2743 EXC_VIRT_BEGIN(altivec_assist, 0x5700, 0x100)
2745 EXC_VIRT_END(altivec_assist, 0x5700, 0x100)
2760 IVEC=0x1800
2764 EXC_REAL_BEGIN(cbe_thermal, 0x1800, 0x100)
2765 GEN_INT_ENTRY cbe_thermal, virt=0
2766 EXC_REAL_END(cbe_thermal, 0x1800, 0x100)
2767 EXC_VIRT_NONE(0x5800, 0x100)
2775 EXC_REAL_NONE(0x1800, 0x100)
2776 EXC_VIRT_NONE(0x5800, 0x100)
2783 IVEC=0x900
2784 ISTACK=0
2785 ICFAR=0
2807 li r9,0
2812 EXCEPTION_RESTORE_REGS hsrr=0
2827 .macro MASKED_INTERRUPT hsrr=0
2845 0: tdnei r9,0
2846 EMIT_WARN_ENTRY 0b,__FILE__,__LINE__,(BUGFLAG_WARNING | BUGFLAG_ONCE)
2855 LOAD_REG_IMMEDIATE(r9, 0x7fffffff)
2876 li r9,0
2884 cmpdi r12,0
2896 mtcrf 0x80,r9
2918 ori 31,31,0
2942 ld r11,(0x80 + 8)*0(r10)
2943 ld r11,(0x80 + 8)*1(r10)
2944 ld r11,(0x80 + 8)*2(r10)
2945 ld r11,(0x80 + 8)*3(r10)
2946 ld r11,(0x80 + 8)*4(r10)
2947 ld r11,(0x80 + 8)*5(r10)
2948 ld r11,(0x80 + 8)*6(r10)
2949 ld r11,(0x80 + 8)*7(r10)
2950 addi r10,r10,0x80*8
2970 * puts 0 in the pt_regs, CTR can be clobbered for the same reason.
2973 li r10,0
3043 ld r11,(0x80 + 8)*0(r10)
3044 ld r11,(0x80 + 8)*1(r10)
3045 ld r11,(0x80 + 8)*2(r10)
3046 ld r11,(0x80 + 8)*3(r10)
3047 ld r11,(0x80 + 8)*4(r10)
3048 ld r11,(0x80 + 8)*5(r10)
3049 ld r11,(0x80 + 8)*6(r10)
3050 ld r11,(0x80 + 8)*7(r10)
3051 addi r10,r10,0x80*8
3055 li r9,0
3056 li r10,0
3057 li r11,0
3095 * handlers, so that they are copied to real address 0x100 when running
3097 * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch
3116 0: mflr r3
3117 addi r3,r3,(1f - 0b)
3130 0: mflr r3
3131 addi r3,r3,(1f - 0b)