Lines Matching +full:machine +full:- +full:mode
1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * Copyright 2009-2010 Freescale Semiconductor, Inc.
12 #include <asm/ppc-opcode.h>
14 /* Machine State Register (MSR) Fields */
16 #define MSR_UCLE_LG 26 /* User-mode cache lock enable */
23 #define MSR_CM_LG 31 /* Computation Mode (0=32-bit, 1=64-bit) */
129 #define SPRN_MCARU 0x239 /* Machine Check Address Register Upper */
130 #define SPRN_MCSRR0 0x23A /* Machine Check Save and Restore Register 0 */
131 #define SPRN_MCSRR1 0x23B /* Machine Check Save and Restore Register 1 */
132 #define SPRN_MCSR 0x23C /* Machine Check Status Register */
133 #define SPRN_MCAR 0x23D /* Machine Check Address Register */
160 #define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
161 #define SPRN_SLER 0x3BB /* Little-endian real mode */
197 #define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */
209 #define MCSR_MCS 0x80000000 /* Machine Check Summary */
214 #define MCSR_ICP 0x04000000 /* I-Cache Parity Error */
215 #define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */
216 #define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */
217 #define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */
221 #define PPC47x_MCSR_IPR 0x00400000 /* Imprecise Machine Check Exception */
225 #define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */
226 #define MCSR_ICPERR 0x40000000UL /* I-Cache Parity Error */
229 #define MCSR_DCP_PERR 0x20000000UL /* D-Cache Push Parity Error */
230 #define MCSR_DCPERR 0x10000000UL /* D-Cache Parity Error */
241 #define MCSR_DCPERR_MC 0x20000000UL /* D-Cache Parity Error */
243 #define MCSR_NMI 0x00100000UL /* Non-Maskable Interrupt */
265 #define HID1_ASTME 0x00002000 /* Address bus streaming mode enable */
267 #define HID1_MPXTT 0x00000400 /* MPX re-map transfer type */
294 #define ESR_MCI 0x80000000 /* Machine Check - Instruction */
295 #define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */
296 #define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */
297 #define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */
298 #define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */
299 #define ESR_PIL 0x08000000 /* Program Exception - Illegal */
300 #define ESR_PPR 0x04000000 /* Program Exception - Privileged */
301 #define ESR_PTR 0x02000000 /* Program Exception - Trap */
303 #define ESR_DST 0x00800000 /* Storage Exception - Data miss */
304 #define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */
313 #define DBCR0_EDM 0x80000000 /* External Debug Mode */
314 #define DBCR0_IDM 0x40000000 /* Internal Debug Mode */
341 #define dbcr_dac(task) ((task)->thread.debug.dbcr0)
358 #define DBCR1_IAC12M 0x00800000 /* Instr Addr 1-2 range enable */
359 #define DBCR1_IAC12MX 0x00C00000 /* Instr Addr 1-2 range eXclusive */
360 #define DBCR1_IAC12AT 0x00010000 /* Instr Addr 1-2 range Toggle */
371 #define DBCR1_IAC34M 0x00000080 /* Instr Addr 3-4 range enable */
372 #define DBCR1_IAC34MX 0x000000C0 /* Instr Addr 3-4 range eXclusive */
373 #define DBCR1_IAC34AT 0x00000001 /* Instr Addr 3-4 range Toggle */
375 #define dbcr_iac_range(task) ((task)->thread.debug.dbcr1)
378 #define DBCR_IAC12MODE DBCR1_IAC12MX /* IAC 1-2 Mode Bits */
381 #define DBCR_IAC34MODE DBCR1_IAC34MX /* IAC 3-4 Mode Bits */
388 #define DBCR2_DAC12M 0x00800000 /* DAC 1-2 range enable */
389 #define DBCR2_DAC12MM 0x00400000 /* DAC 1-2 Mask mode*/
390 #define DBCR2_DAC12MX 0x00C00000 /* DAC 1-2 range eXclusive */
391 #define DBCR2_DAC12MODE 0x00C00000 /* DAC 1-2 Mode Bits */
392 #define DBCR2_DAC12A 0x00200000 /* DAC 1-2 Asynchronous */
393 #define DBCR2_DVC1M 0x000C0000 /* Data Value Comp 1 Mode */
395 #define DBCR2_DVC2M 0x00030000 /* Data Value Comp 2 Mode */
463 #define DCWR_COPY 0 /* Copy-back */
464 #define DCWR_WRITE 1 /* Write-through */
498 #define L2CSR0_L2CM 0x03000000 /* L2 Cache Coherency Mode */
524 #define SPRN_EPCR_ICM 0x02000000 /* Interrupt computation mode
526 #define SPRN_EPCR_GICM 0x01000000 /* Guest Interrupt Comp. mode */