Lines Matching full:register
3 * Contains register definitions common to the Book E PowerPC
14 /* Machine State Register (MSR) Fields */
48 #define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */
49 #define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */
50 #define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */
51 #define SPRN_SPRG3R 0x103 /* Special Purpose Register General 3 Read */
52 #define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */
53 #define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */
54 #define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */
55 #define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */
56 #define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */
57 #define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */
58 #define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */
59 #define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */
60 #define SPRN_EPCR 0x133 /* Embedded Processor Control Register */
61 #define SPRN_DBCR2 0x136 /* Debug Control Register 2 */
62 #define SPRN_DBCR4 0x233 /* Debug Control Register 4 */
63 #define SPRN_MSRP 0x137 /* MSR Protect Register */
66 #define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */
67 #define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */
69 #define SPRN_MAS8 0x155 /* MMU Assist Register 8 */
70 #define SPRN_TLB0PS 0x158 /* TLB 0 Page Size Register */
71 #define SPRN_TLB1PS 0x159 /* TLB 1 Page Size Register */
72 #define SPRN_MAS5_MAS6 0x15c /* MMU Assist Register 5 || 6 */
73 #define SPRN_MAS8_MAS1 0x15d /* MMU Assist Register 8 || 1 */
79 #define SPRN_MAS7_MAS3 0x174 /* MMU Assist Register 7 || 3 */
80 #define SPRN_MAS0_MAS1 0x175 /* MMU Assist Register 0 || 1 */
86 #define SPRN_GESR 0x17F /* Guest Exception Syndrome Register */
87 #define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */
88 #define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */
89 #define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */
90 #define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */
91 #define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */
92 #define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */
93 #define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */
94 #define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */
95 #define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */
96 #define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */
97 #define SPRN_IVOR10 0x19A /* Interrupt Vector Offset Register 10 */
98 #define SPRN_IVOR11 0x19B /* Interrupt Vector Offset Register 11 */
99 #define SPRN_IVOR12 0x19C /* Interrupt Vector Offset Register 12 */
100 #define SPRN_IVOR13 0x19D /* Interrupt Vector Offset Register 13 */
101 #define SPRN_IVOR14 0x19E /* Interrupt Vector Offset Register 14 */
102 #define SPRN_IVOR15 0x19F /* Interrupt Vector Offset Register 15 */
103 #define SPRN_IVOR38 0x1B0 /* Interrupt Vector Offset Register 38 */
104 #define SPRN_IVOR39 0x1B1 /* Interrupt Vector Offset Register 39 */
105 #define SPRN_IVOR40 0x1B2 /* Interrupt Vector Offset Register 40 */
106 #define SPRN_IVOR41 0x1B3 /* Interrupt Vector Offset Register 41 */
107 #define SPRN_IVOR42 0x1B4 /* Interrupt Vector Offset Register 42 */
116 #define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */
117 #define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */
118 #define SPRN_L1CFG0 0x203 /* L1 Cache Configure Register 0 */
119 #define SPRN_L1CFG1 0x204 /* L1 Cache Configure Register 1 */
123 #define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */
124 #define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */
125 #define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */
126 #define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */
127 #define SPRN_IVOR36 0x214 /* Interrupt Vector Offset Register 36 */
128 #define SPRN_IVOR37 0x215 /* Interrupt Vector Offset Register 37 */
129 #define SPRN_MCARU 0x239 /* Machine Check Address Register Upper */
130 #define SPRN_MCSRR0 0x23A /* Machine Check Save and Restore Register 0 */
131 #define SPRN_MCSRR1 0x23B /* Machine Check Save and Restore Register 1 */
132 #define SPRN_MCSR 0x23C /* Machine Check Status Register */
133 #define SPRN_MCAR 0x23D /* Machine Check Address Register */
134 #define SPRN_DSRR0 0x23E /* Debug Save and Restore Register 0 */
135 #define SPRN_DSRR1 0x23F /* Debug Save and Restore Register 1 */
136 #define SPRN_SPRG8 0x25C /* Special Purpose Register General 8 */
137 #define SPRN_SPRG9 0x25D /* Special Purpose Register General 9 */
138 #define SPRN_L1CSR2 0x25E /* L1 Cache Control and Status Register 2 */
139 #define SPRN_MAS0 0x270 /* MMU Assist Register 0 */
140 #define SPRN_MAS1 0x271 /* MMU Assist Register 1 */
141 #define SPRN_MAS2 0x272 /* MMU Assist Register 2 */
142 #define SPRN_MAS3 0x273 /* MMU Assist Register 3 */
143 #define SPRN_MAS4 0x274 /* MMU Assist Register 4 */
144 #define SPRN_MAS5 0x153 /* MMU Assist Register 5 */
145 #define SPRN_MAS6 0x276 /* MMU Assist Register 6 */
146 #define SPRN_PID1 0x279 /* Process ID Register 1 */
147 #define SPRN_PID2 0x27A /* Process ID Register 2 */
148 #define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */
149 #define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */
150 #define SPRN_TLB2CFG 0x2B2 /* TLB 2 Config Register */
151 #define SPRN_TLB3CFG 0x2B3 /* TLB 3 Config Register */
152 #define SPRN_EPR 0x2BE /* External Proxy Register */
153 #define SPRN_CCR1 0x378 /* Core Configuration Register 1 */
154 #define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */
155 #define SPRN_MMUCR 0x3B2 /* MMU Control Register */
156 #define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */
159 #define SPRN_SGR 0x3B9 /* Storage Guarded Register */
160 #define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
162 #define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */
163 #define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */
164 #define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */
165 #define SPRN_L1CSR0 0x3F2 /* L1 Cache Control and Status Register 0 */
166 #define SPRN_L1CSR1 0x3F3 /* L1 Cache Control and Status Register 1 */
167 #define SPRN_MMUCSR0 0x3F4 /* MMU Control and Status Register 0 */
168 #define SPRN_MMUCFG 0x3F7 /* MMU Configuration Register */
170 #define SPRN_L2CSR0 0x3F9 /* L2 Data Cache Control and Status Register 0 */
171 #define SPRN_L2CSR1 0x3FA /* L2 Data Cache Control and Status Register 1 */
172 #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
173 #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
174 #define SPRN_PWRMGTCR0 0x3FB /* Power management control register 0 */
175 #define SPRN_SVR 0x3FF /* System Version Register */
180 #define SPRN_CSRR0 0x03A /* Critical Save and Restore Register 0 */
181 #define SPRN_CSRR1 0x03B /* Critical Save and Restore Register 1 */
182 #define SPRN_DEAR 0x03D /* Data Error Address Register */
183 #define SPRN_ESR 0x03E /* Exception Syndrome Register */
184 #define SPRN_PIR 0x11E /* Processor Identification Register */
185 #define SPRN_DBSR 0x130 /* Debug Status Register */
186 #define SPRN_DBCR0 0x134 /* Debug Control Register 0 */
187 #define SPRN_DBCR1 0x135 /* Debug Control Register 1 */
192 #define SPRN_TSR 0x150 /* Timer Status Register */
193 #define SPRN_TCR 0x154 /* Timer Control Register */
194 #define SPRN_HACOP 0x15F /* Hypervisor Available Coprocessor Register */
563 #define TMRN_TMCFG0 16 /* Thread Management Configuration Register 0 */
569 #define TMRN_IMSR0 0x120 /* Initial MSR Register 0 (e6500) */
570 #define TMRN_IMSR1 0x121 /* Initial MSR Register 1 (e6500) */
571 #define TMRN_INIA0 0x140 /* Next Instruction Address Register 0 */
572 #define TMRN_INIA1 0x141 /* Next Instruction Address Register 1 */
573 #define SPRN_TENSR 0x1b5 /* Thread Enable Status Register */
574 #define SPRN_TENS 0x1b6 /* Thread Enable Set Register */
575 #define SPRN_TENC 0x1b7 /* Thread Enable Clear Register */