Lines Matching +full:p9 +full:- +full:scom
1 /* SPDX-License-Identifier: GPL-2.0 */
6 * number used in the Programming Environments Manual For 32-Bit
17 #include <asm/asm-const.h>
18 #include <asm/feature-fixups.h>
74 /* so tests for these bits fail on 32-bit */
116 #define MSR_TS_N 0 /* Non-transactional */
161 /* Power Management - Processor Stop Status and Control Register Fields */
165 #define PSSCR_PSLL_MASK 0x000F0000 /* Power-Saving Level Limit */
169 #define PSSCR_PLS 0xf000000000000000 /* Power-saving Level Status */
171 #define PSSCR_GUEST_VIS 0xf0000000000003ffUL /* Guest-visible PSSCR fields */
172 #define PSSCR_FAKE_SUSPEND 0x00000400 /* Fake-suspend bit (P9 DD2.2) */
173 #define PSSCR_FAKE_SUSPEND_LG 10 /* Fake-suspend bit position */
181 #define FPSCR_ZX 0x04000000 /* Zero-divide exception summary */
184 #define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */
201 #define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */
252 #define TEXASR_FC_LG (63 - 7) /* Failure Code */
253 #define TEXASR_AB_LG (63 - 31) /* Abort */
254 #define TEXASR_SU_LG (63 - 32) /* Suspend */
255 #define TEXASR_HV_LG (63 - 34) /* Hypervisor state*/
256 #define TEXASR_PR_LG (63 - 35) /* Privilege level */
257 #define TEXASR_FS_LG (63 - 36) /* failure summary */
258 #define TEXASR_EX_LG (63 - 37) /* TFIAR exact bit */
259 #define TEXASR_ROT_LG (63 - 38) /* ROT bit */
310 #define DSISR_ATTR_CONFLICT 0x20000000 /* P9: Process vs. Partition attr */
319 #define DSISR_UNSUPP_MMU 0x00080000 /* P9: Unsupported MMU config */
320 #define DSISR_SET_RC 0x00040000 /* P9: Failed setting of R/C bits */
321 #define DSISR_PRTABLE_FAULT 0x00020000 /* P9: Fault on process table */
323 #define DSISR_BAD_COPYPASTE 0x00000008 /* P9: Copy/Paste on wrong memtype */
324 #define DSISR_BAD_AMO 0x00000004 /* P9: Incorrect AMO opcode */
330 * indicates an attempt at executing from a no-execute PTE
381 #define SPRN_HDEXCR_RO 0x1C7 /* Hypervisor DEXCR (non-privileged, readonly) */
382 #define SPRN_HASHKEYR 0x1D4 /* Non-privileged hashst/hashchk key register */
384 #define SPRN_DEXCR_RO 0x32C /* DEXCR (non-privileged, readonly) */
390 #define DEXCR_PR_NPHIE 0x04000000UL /* 5: Non-Privileged Hash Instruction Enable */
402 #define SPRN_RWMR 0x375 /* Region-Weighting Mode Register */
455 #define LPCR_ONL ASM_CONST(0x0000000000040000) /* online - PURR/SPURR count */
463 #define LPCR_PECE_HVEE ASM_CONST(0x0000400000000000) /* P9 Wakeup on HV interrupts */
474 #define LPCR_HVICE ASM_CONST(0x0000000000000002) /* P9: HV interrupt enable */
482 #define HMER_DEBUG_TRIG (1ul << (63 - 17)) /* Debug trigger */
485 #define PCR_VEC_DIS (__MASK(63-0)) /* Vec. disable (bit NA since POWER8) */
486 #define PCR_VSX_DIS (__MASK(63-1)) /* VSX disable (bit NA since POWER8) */
487 #define PCR_TM_DIS (__MASK(63-2)) /* Trans. memory disable (POWER8) */
488 #define PCR_MMA_DIS (__MASK(63-3)) /* Matrix-Multiply Accelerator */
555 #define HID0_HDICE_SH (63 - 23) /* 970 HDEC interrupt enable */
561 #define HID0_TBEN (1<<26) /* Timebase enable - 745x */
564 #define HID0_STEN (1<<24) /* Software table search enable - 745x */
565 #define HID0_HIGH_BAT (1<<23) /* Enable high BATs - 7455 */
570 #define HID0_BHTCLR (1<<18) /* Clear branch history table - 7450 */
571 #define HID0_XAEN (1<<17) /* Extended addressing enable - 7450 */
572 #define HID0_NHR (1<<16) /* Not hard reset (software bit-7450)*/
584 #define HID0_LRSTK (1<<4) /* Link register stack - 745x */
587 #define HID0_FOLD (1<<3) /* Branch Folding enable - 745x */
590 #define HID0_NOPDST (1<<1) /* No-op dst, dstt, etc. instr. */
591 #define HID0_NOPTI (1<<0) /* No-op dcbt and dcbst instr. */
600 #define HID0_POWER9_RADIX __MASK(63 - 8)
623 #define HID4_LPES0 (1ul << (63-0)) /* LPAR env. sel. bit 0 */
624 #define HID4_RMLS2_SH (63 - 2) /* Real mode limit bottom 2 bits */
625 #define HID4_LPID5_SH (63 - 6) /* partition ID bottom 4 bits */
626 #define HID4_RMOR_SH (63 - 22) /* real mode offset (16 bits) */
628 #define HID4_LPES1 (1 << (63-57)) /* LPAR env. sel. bit 1 */
629 #define HID4_RMLS0_SH (63 - 58) /* Real mode limit top bit */
695 #define L2CR_L2WT 0x00080000 /* L2 write-through */
719 #define L3CR_L3PSP 0x0000e000 /* L3 P-clock sample point */
724 #define L3CR_L3NIRCA 0x00000080 /* L3 non-integer ratio clock adj. */
768 * PPC (64-bit) bits 33-36,42-47 are interrupt dependent, the others are
770 * bit 62 (RI) from MSR. Don't use PPC_BITMASK for this because 32-bit uses
777 #define SRR1_ISI_N_G_OR_CIP 0x10000000 /* ISI: Access is no-exec or G or CI for a prefixed instru…
784 #define SRR1_WAKEHVI 0x00240000 /* Hypervisor Virtualization Interrupt (P9) */
804 #define SRR1_BOUNDARY 0x10000000 /* Prefixed instruction crosses 64-byte boundary */
852 #define SPRN_SCOMC 0x114 /* SCOM Access Control */
853 #define SPRN_SCOMD 0x115 /* SCOM Access DATA */
872 #define MMCR0_PMCC_U6 0x00080000UL /* PMC1-6 are R/W by user (PR) */
897 #define MMCRA_SLOT 0x07000000UL /* SLOT bits (37-39) */
917 #define SPRN_WORT 895 /* Workload optimization register - thread */
918 #define SPRN_WORC 863 /* Workload optimization register - core */
1040 #else /* 32-bit */
1084 * All 64-bit:
1085 * - SPRG1 stores PACA pointer except 64-bit server in
1088 * 64-bit server:
1089 * - SPRG0 scratch for TM recheckpoint/reclaim (reserved for HV on Power4)
1090 * - SPRG2 scratch for exception vectors
1091 * - SPRG3 CPU and NUMA node for VDSO getcpu (user visible)
1092 * - HSPRG0 stores PACA in HV mode
1093 * - HSPRG1 scratch for "HV" exceptions
1095 * 64-bit embedded
1096 * - SPRG0 generic exception scratch
1097 * - SPRG2 TLB exception stack
1098 * - SPRG3 critical exception scratch (user visible, sorry!)
1099 * - SPRG4 unused (user visible)
1100 * - SPRG6 TLB miss scratch (user visible, sorry !)
1101 * - SPRG7 CPU and NUMA node for VDSO getcpu (user visible)
1102 * - SPRG8 machine check exception scratch
1103 * - SPRG9 debug exception scratch
1105 * All 32-bit:
1106 * - SPRG3 current thread_struct physical addr pointer
1109 * 32-bit classic:
1110 * - SPRG0 scratch for exception vectors
1111 * - SPRG1 scratch for exception vectors
1112 * - SPRG2 indicator that we are in RTAS
1113 * - SPRG4 (603 only) pseudo TLB LRU data
1115 * 32-bit 440 and FSL BookE:
1116 * - SPRG0 scratch for exception vectors
1117 * - SPRG1 scratch for exception vectors (*)
1118 * - SPRG2 scratch for crit interrupts handler
1119 * - SPRG4 scratch for exception vectors
1120 * - SPRG5 scratch for exception vectors
1121 * - SPRG6 scratch for machine check handler
1122 * - SPRG7 scratch for exception vectors
1123 * - SPRG9 scratch for debug vectors (e500 only)
1130 * 32-bit 8xx:
1131 * - SPRG0 scratch for exception vectors
1132 * - SPRG1 scratch for exception vectors
1133 * - SPRG2 scratch for exception vectors
1254 * IBM has further subdivided the standard PowerPC 16-bit version and
1322 /* 64-bit processors */