Lines Matching +full:system +full:- +full:control
1 /* SPDX-License-Identifier: GPL-2.0-only */
18 u32 rcr; /* Reset Control Register */
19 u32 rcer; /* Reset Control Enable Register */
23 * Clock Control Module
26 u32 spmr; /* System PLL Mode Register */
27 u32 sccr1; /* System Clock Control Register 1 */
28 u32 sccr2; /* System Clock Control Register 2 */
29 u32 scfr1; /* System Clock Frequency Register 1 */
30 u32 scfr2; /* System Clock Frequency Register 2 */
31 u32 scfr2s; /* System Clock Frequency Shadow Register 2 */
33 u32 psc_ccr[12]; /* PSC Clock Control Registers */
34 u32 spccr; /* SPDIF Clock Control Register */
35 u32 cccr; /* CFM Clock Control Register */
36 u32 dccr; /* DIU Clock Control Register */
37 u32 mscan_ccr[4]; /* MSCAN Clock Control Registers */
40 u32 scfr3; /* System Clock Frequency Register 3 */
42 u32 spll_lock_cnt; /* System PLL Lock Counter */
51 u32 cs_ctrl; /* CS Control Register */
53 u32 burst_ctrl; /* CS Burst Control Register */
54 u32 deadcycle_ctrl; /* CS Deadcycle Control Register */
55 u32 holdcycle_ctrl; /* CS Holdcycle Control Register */
67 u32 ctrl; /* SCLPC Control Register */
73 u32 emb_pc; /* EMB Pause Control Register */
77 u32 fifo_ctrl; /* LPC RX/TX FIFO Control Register */