Lines Matching full:register

11 	u32	rcwlr;	/* Reset Configuration Word Low Register */
12 	u32	rcwhr;	/* Reset Configuration Word High Register */
15 	u32	rsr;	/* Reset Status Register */
16 	u32	rmr;	/* Reset Mode Register */
17 	u32	rpr;	/* Reset Protection Register */
18 	u32	rcr;	/* Reset Control Register */
19 	u32	rcer;	/* Reset Control Enable Register */
26 	u32	spmr;	/* System PLL Mode Register */
27 	u32	sccr1;	/* System Clock Control Register 1 */
28 	u32	sccr2;	/* System Clock Control Register 2 */
29 	u32	scfr1;	/* System Clock Frequency Register 1 */
30 	u32	scfr2;	/* System Clock Frequency Register 2 */
31 	u32	scfr2s;	/* System Clock Frequency Shadow Register 2 */
32 	u32	bcr;	/* Bread Crumb Register */
34 	u32	spccr;	/* SPDIF Clock Control Register */
35 	u32	cccr;	/* CFM Clock Control Register */
36 	u32	dccr;	/* DIU Clock Control Register */
40 	u32	scfr3;		/* System Clock Frequency Register 3 */
51 	u32	cs_ctrl;	/* CS Control Register */
52 	u32	cs_status;	/* CS Status Register */
53 	u32	burst_ctrl;	/* CS Burst Control Register */
54 	u32	deadcycle_ctrl;	/* CS Deadcycle Control Register */
55 	u32	holdcycle_ctrl;	/* CS Holdcycle Control Register */
56 	u32	alt;		/* Address Latch Timing Register */
65 	u32	pkt_size;	/* SCLPC Packet Size Register */
66 	u32	start_addr;	/* SCLPC Start Address Register */
67 	u32	ctrl;		/* SCLPC Control Register */
68 	u32	enable;		/* SCLPC Enable Register */
70 	u32	status;		/* SCLPC Status Register */
71 	u32	bytes_done;	/* SCLPC Bytes Done Register */
72 	u32	emb_sc;		/* EMB Share Counter Register */
73 	u32	emb_pc;		/* EMB Pause Control Register */
75 	u32	data_word;	/* LPC RX/TX FIFO Data Word Register */
76 	u32	fifo_status;	/* LPC RX/TX FIFO Status Register */
77 	u32	fifo_ctrl;	/* LPC RX/TX FIFO Control Register */
78 	u32	fifo_alarm;	/* LPC RX/TX FIFO Alarm Register */