Lines Matching +full:internal +full:- +full:clock
1 /* SPDX-License-Identifier: GPL-2.0 */
7 * All CPM control and status is available through the CPM2 internal
27 /* Device sub-block and page codes.
72 /* CPM2-specific opcodes (see cpm.h for common opcodes)
109 * oversampled clock.
153 * get some microcode patches :-).
154 * The parameter ram space for the SMCs is fifty-some bytes, and
169 uint smc_rstate; /* Internal */
170 uint smc_idp; /* Internal */
171 ushort smc_rbptr; /* Internal */
172 ushort smc_ibc; /* Internal */
173 uint smc_rxtmp; /* Internal */
174 uint smc_tstate; /* Internal */
175 uint smc_tdp; /* Internal */
176 ushort smc_tbptr; /* Internal */
177 ushort smc_tbc; /* Internal */
178 uint smc_txtmp; /* Internal */
188 /* SMC uart mode register (Internal memory map).
311 uint scc_rstate; /* Internal */
312 uint scc_idp; /* Internal */
313 ushort scc_rbptr; /* Internal */
314 ushort scc_ibc; /* Internal */
315 uint scc_rxtmp; /* Internal */
316 uint scc_tstate; /* Internal */
317 uint scc_tdp; /* Internal */
318 ushort scc_tbptr; /* Internal */
319 ushort scc_tbc; /* Internal */
320 uint scc_txtmp; /* Internal */
321 uint scc_rcrc; /* Internal */
322 uint scc_tcrc; /* Internal */
353 uint sen_tbuf0data0; /* Save area 0 - current frame */
354 uint sen_tbuf0data1; /* Save area 1 - current frame */
355 uint sen_tbuf0rba; /* Internal */
356 uint sen_tbuf0crc; /* Internal */
357 ushort sen_tbuf0bcnt; /* Internal */
365 uint sen_tbuf1data0; /* Save area 0 - current frame */
366 uint sen_tbuf1data1; /* Save area 1 - current frame */
367 uint sen_tbuf1rba; /* Internal */
368 uint sen_tbuf1crc; /* Internal */
369 ushort sen_tbuf1bcnt; /* Internal */
514 ushort fcc_riptr; /* Rx Internal temp pointer */
515 ushort fcc_tiptr; /* Tx Internal temp pointer */
522 uint fcc_rdptr; /* RxBD internal data pointer */
527 uint fcc_tdptr; /* TxBD internal data pointer */
528 uint fcc_rbptr; /* Rx BD Internal buf pointer */
529 uint fcc_tbptr; /* Tx BD Internal buf pointer */
540 uint fen_statbuf; /* Internal status buffer */
551 uint fen_gaddrh; /* Group address filter, high 32-bits */
552 uint fen_gaddrl; /* Group address filter, low 32-bits */
560 ushort fen_ibdcount; /* Internal BD counter */
561 ushort fen_ibdstart; /* Internal BD start pointer */
562 ushort fen_ibdend; /* Internal BD end pointer */
563 ushort fen_txlen; /* Internal Tx frame length counter */
564 uint fen_ibdbase[8]; /* Internal use */
577 ushort fen_maxd; /* internal max DMA count */
578 ushort fen_dmacnt; /* internal DMA counter */
593 uint fen_cambuf; /* Internal CAM buffer pointer */
623 #define FCC_PSMR_ENCRC ((uint)0x00000080) /* Use 32-bit CRC */
633 uint iic_rstate; /* Internal */
634 uint iic_rdp; /* Internal */
635 ushort iic_rbptr; /* Internal */
636 ushort iic_rbc; /* Internal */
637 uint iic_rxtmp; /* Internal */
638 uint iic_tstate; /* Internal */
639 uint iic_tdp; /* Internal */
640 ushort iic_tbptr; /* Internal */
641 ushort iic_tbc; /* Internal */
642 uint iic_txtmp; /* Internal */
652 ushort buf_inv; /* internal buffer inventory */
653 ushort ss_max; /* steady-state maximum transfer size */
654 ushort dpr_in_ptr; /* write pointer inside the internal buffer */
656 ushort dpr_out_ptr; /* read pointer inside the internal buffer */
662 uint bd_cnt; /* internal byte count */
663 uint s_ptr; /* source internal data pointer */
664 uint d_ptr; /* destination internal data pointer */
665 uint istate; /* internal state */
666 u_char res1[20]; /* pad to 64-byte length */
671 #define IDMA_DCM_FB ((ushort)0x8000) /* fly-by mode */
675 #define IDMA_DCM_DMA_WRAP_64 ((ushort)0x0000) /* 64-byte DMA xfer buffer */
676 #define IDMA_DCM_DMA_WRAP_128 ((ushort)0x0040) /* 128-byte DMA xfer buffer */
677 #define IDMA_DCM_DMA_WRAP_256 ((ushort)0x0080) /* 256-byte DMA xfer buffer */
678 #define IDMA_DCM_DMA_WRAP_512 ((ushort)0x00c0) /* 512-byte DMA xfer buffer */
679 #define IDMA_DCM_DMA_WRAP_1024 ((ushort)0x0100) /* 1024-byte DMA xfer buffer */
680 #define IDMA_DCM_DMA_WRAP_2048 ((ushort)0x0140) /* 2048-byte DMA xfer buffer */
686 #define IDMA_DCM_SD_MEM2MEM ((ushort)0x0000) /* memory-to-memory xfer */
687 #define IDMA_DCM_SD_PER2MEM ((ushort)0x0002) /* peripheral-to-memory xfer */
688 #define IDMA_DCM_SD_MEM2PER ((ushort)0x0001) /* memory-to-peripheral xfer */
709 #define IDMA_BD_DBO_LE ((uint)0x00040000) /* little-end dest byte order */
710 #define IDMA_BD_DBO_BE ((uint)0x00080000) /* big-end dest byte order */
713 #define IDMA_BD_SBO_LE ((uint)0x00000800) /* little-end src byte order */
714 #define IDMA_BD_SBO_BE ((uint)0x00001000) /* big-end src byte order */
717 /* per-channel IDMA registers
774 /*-----------------------------------------------------------------------
775 * CMXFCR - CMX FCC Clock Route Register
778 #define CMXFCR_RF1CS_MSK 0x38000000 /* Receive FCC1 Clock Source Mask */
779 #define CMXFCR_TF1CS_MSK 0x07000000 /* Transmit FCC1 Clock Source Mask */
781 #define CMXFCR_RF2CS_MSK 0x00380000 /* Receive FCC2 Clock Source Mask */
782 #define CMXFCR_TF2CS_MSK 0x00070000 /* Transmit FCC2 Clock Source Mask */
784 #define CMXFCR_RF3CS_MSK 0x00003800 /* Receive FCC3 Clock Source Mask */
785 #define CMXFCR_TF3CS_MSK 0x00000700 /* Transmit FCC3 Clock Source Mask */
787 #define CMXFCR_RF1CS_BRG5 0x00000000 /* Receive FCC1 Clock Source is BRG5 */
788 #define CMXFCR_RF1CS_BRG6 0x08000000 /* Receive FCC1 Clock Source is BRG6 */
789 #define CMXFCR_RF1CS_BRG7 0x10000000 /* Receive FCC1 Clock Source is BRG7 */
790 #define CMXFCR_RF1CS_BRG8 0x18000000 /* Receive FCC1 Clock Source is BRG8 */
791 #define CMXFCR_RF1CS_CLK9 0x20000000 /* Receive FCC1 Clock Source is CLK9 */
792 #define CMXFCR_RF1CS_CLK10 0x28000000 /* Receive FCC1 Clock Source is CLK10 */
793 #define CMXFCR_RF1CS_CLK11 0x30000000 /* Receive FCC1 Clock Source is CLK11 */
794 #define CMXFCR_RF1CS_CLK12 0x38000000 /* Receive FCC1 Clock Source is CLK12 */
796 #define CMXFCR_TF1CS_BRG5 0x00000000 /* Transmit FCC1 Clock Source is BRG5 */
797 #define CMXFCR_TF1CS_BRG6 0x01000000 /* Transmit FCC1 Clock Source is BRG6 */
798 #define CMXFCR_TF1CS_BRG7 0x02000000 /* Transmit FCC1 Clock Source is BRG7 */
799 #define CMXFCR_TF1CS_BRG8 0x03000000 /* Transmit FCC1 Clock Source is BRG8 */
800 #define CMXFCR_TF1CS_CLK9 0x04000000 /* Transmit FCC1 Clock Source is CLK9 */
801 #define CMXFCR_TF1CS_CLK10 0x05000000 /* Transmit FCC1 Clock Source is CLK10 */
802 #define CMXFCR_TF1CS_CLK11 0x06000000 /* Transmit FCC1 Clock Source is CLK11 */
803 #define CMXFCR_TF1CS_CLK12 0x07000000 /* Transmit FCC1 Clock Source is CLK12 */
805 #define CMXFCR_RF2CS_BRG5 0x00000000 /* Receive FCC2 Clock Source is BRG5 */
806 #define CMXFCR_RF2CS_BRG6 0x00080000 /* Receive FCC2 Clock Source is BRG6 */
807 #define CMXFCR_RF2CS_BRG7 0x00100000 /* Receive FCC2 Clock Source is BRG7 */
808 #define CMXFCR_RF2CS_BRG8 0x00180000 /* Receive FCC2 Clock Source is BRG8 */
809 #define CMXFCR_RF2CS_CLK13 0x00200000 /* Receive FCC2 Clock Source is CLK13 */
810 #define CMXFCR_RF2CS_CLK14 0x00280000 /* Receive FCC2 Clock Source is CLK14 */
811 #define CMXFCR_RF2CS_CLK15 0x00300000 /* Receive FCC2 Clock Source is CLK15 */
812 #define CMXFCR_RF2CS_CLK16 0x00380000 /* Receive FCC2 Clock Source is CLK16 */
814 #define CMXFCR_TF2CS_BRG5 0x00000000 /* Transmit FCC2 Clock Source is BRG5 */
815 #define CMXFCR_TF2CS_BRG6 0x00010000 /* Transmit FCC2 Clock Source is BRG6 */
816 #define CMXFCR_TF2CS_BRG7 0x00020000 /* Transmit FCC2 Clock Source is BRG7 */
817 #define CMXFCR_TF2CS_BRG8 0x00030000 /* Transmit FCC2 Clock Source is BRG8 */
818 #define CMXFCR_TF2CS_CLK13 0x00040000 /* Transmit FCC2 Clock Source is CLK13 */
819 #define CMXFCR_TF2CS_CLK14 0x00050000 /* Transmit FCC2 Clock Source is CLK14 */
820 #define CMXFCR_TF2CS_CLK15 0x00060000 /* Transmit FCC2 Clock Source is CLK15 */
821 #define CMXFCR_TF2CS_CLK16 0x00070000 /* Transmit FCC2 Clock Source is CLK16 */
823 #define CMXFCR_RF3CS_BRG5 0x00000000 /* Receive FCC3 Clock Source is BRG5 */
824 #define CMXFCR_RF3CS_BRG6 0x00000800 /* Receive FCC3 Clock Source is BRG6 */
825 #define CMXFCR_RF3CS_BRG7 0x00001000 /* Receive FCC3 Clock Source is BRG7 */
826 #define CMXFCR_RF3CS_BRG8 0x00001800 /* Receive FCC3 Clock Source is BRG8 */
827 #define CMXFCR_RF3CS_CLK13 0x00002000 /* Receive FCC3 Clock Source is CLK13 */
828 #define CMXFCR_RF3CS_CLK14 0x00002800 /* Receive FCC3 Clock Source is CLK14 */
829 #define CMXFCR_RF3CS_CLK15 0x00003000 /* Receive FCC3 Clock Source is CLK15 */
830 #define CMXFCR_RF3CS_CLK16 0x00003800 /* Receive FCC3 Clock Source is CLK16 */
832 #define CMXFCR_TF3CS_BRG5 0x00000000 /* Transmit FCC3 Clock Source is BRG5 */
833 #define CMXFCR_TF3CS_BRG6 0x00000100 /* Transmit FCC3 Clock Source is BRG6 */
834 #define CMXFCR_TF3CS_BRG7 0x00000200 /* Transmit FCC3 Clock Source is BRG7 */
835 #define CMXFCR_TF3CS_BRG8 0x00000300 /* Transmit FCC3 Clock Source is BRG8 */
836 #define CMXFCR_TF3CS_CLK13 0x00000400 /* Transmit FCC3 Clock Source is CLK13 */
837 #define CMXFCR_TF3CS_CLK14 0x00000500 /* Transmit FCC3 Clock Source is CLK14 */
838 #define CMXFCR_TF3CS_CLK15 0x00000600 /* Transmit FCC3 Clock Source is CLK15 */
839 #define CMXFCR_TF3CS_CLK16 0x00000700 /* Transmit FCC3 Clock Source is CLK16 */
841 /*-----------------------------------------------------------------------
842 * CMXSCR - CMX SCC Clock Route Register
846 #define CMXSCR_RS1CS_MSK 0x38000000 /* Receive SCC1 Clock Source Mask */
847 #define CMXSCR_TS1CS_MSK 0x07000000 /* Transmit SCC1 Clock Source Mask */
850 #define CMXSCR_RS2CS_MSK 0x00380000 /* Receive SCC2 Clock Source Mask */
851 #define CMXSCR_TS2CS_MSK 0x00070000 /* Transmit SCC2 Clock Source Mask */
854 #define CMXSCR_RS3CS_MSK 0x00003800 /* Receive SCC3 Clock Source Mask */
855 #define CMXSCR_TS3CS_MSK 0x00000700 /* Transmit SCC3 Clock Source Mask */
858 #define CMXSCR_RS4CS_MSK 0x00000038 /* Receive SCC4 Clock Source Mask */
859 #define CMXSCR_TS4CS_MSK 0x00000007 /* Transmit SCC4 Clock Source Mask */
861 #define CMXSCR_RS1CS_BRG1 0x00000000 /* SCC1 Rx Clock Source is BRG1 */
862 #define CMXSCR_RS1CS_BRG2 0x08000000 /* SCC1 Rx Clock Source is BRG2 */
863 #define CMXSCR_RS1CS_BRG3 0x10000000 /* SCC1 Rx Clock Source is BRG3 */
864 #define CMXSCR_RS1CS_BRG4 0x18000000 /* SCC1 Rx Clock Source is BRG4 */
865 #define CMXSCR_RS1CS_CLK11 0x20000000 /* SCC1 Rx Clock Source is CLK11 */
866 #define CMXSCR_RS1CS_CLK12 0x28000000 /* SCC1 Rx Clock Source is CLK12 */
867 #define CMXSCR_RS1CS_CLK3 0x30000000 /* SCC1 Rx Clock Source is CLK3 */
868 #define CMXSCR_RS1CS_CLK4 0x38000000 /* SCC1 Rx Clock Source is CLK4 */
870 #define CMXSCR_TS1CS_BRG1 0x00000000 /* SCC1 Tx Clock Source is BRG1 */
871 #define CMXSCR_TS1CS_BRG2 0x01000000 /* SCC1 Tx Clock Source is BRG2 */
872 #define CMXSCR_TS1CS_BRG3 0x02000000 /* SCC1 Tx Clock Source is BRG3 */
873 #define CMXSCR_TS1CS_BRG4 0x03000000 /* SCC1 Tx Clock Source is BRG4 */
874 #define CMXSCR_TS1CS_CLK11 0x04000000 /* SCC1 Tx Clock Source is CLK11 */
875 #define CMXSCR_TS1CS_CLK12 0x05000000 /* SCC1 Tx Clock Source is CLK12 */
876 #define CMXSCR_TS1CS_CLK3 0x06000000 /* SCC1 Tx Clock Source is CLK3 */
877 #define CMXSCR_TS1CS_CLK4 0x07000000 /* SCC1 Tx Clock Source is CLK4 */
879 #define CMXSCR_RS2CS_BRG1 0x00000000 /* SCC2 Rx Clock Source is BRG1 */
880 #define CMXSCR_RS2CS_BRG2 0x00080000 /* SCC2 Rx Clock Source is BRG2 */
881 #define CMXSCR_RS2CS_BRG3 0x00100000 /* SCC2 Rx Clock Source is BRG3 */
882 #define CMXSCR_RS2CS_BRG4 0x00180000 /* SCC2 Rx Clock Source is BRG4 */
883 #define CMXSCR_RS2CS_CLK11 0x00200000 /* SCC2 Rx Clock Source is CLK11 */
884 #define CMXSCR_RS2CS_CLK12 0x00280000 /* SCC2 Rx Clock Source is CLK12 */
885 #define CMXSCR_RS2CS_CLK3 0x00300000 /* SCC2 Rx Clock Source is CLK3 */
886 #define CMXSCR_RS2CS_CLK4 0x00380000 /* SCC2 Rx Clock Source is CLK4 */
888 #define CMXSCR_TS2CS_BRG1 0x00000000 /* SCC2 Tx Clock Source is BRG1 */
889 #define CMXSCR_TS2CS_BRG2 0x00010000 /* SCC2 Tx Clock Source is BRG2 */
890 #define CMXSCR_TS2CS_BRG3 0x00020000 /* SCC2 Tx Clock Source is BRG3 */
891 #define CMXSCR_TS2CS_BRG4 0x00030000 /* SCC2 Tx Clock Source is BRG4 */
892 #define CMXSCR_TS2CS_CLK11 0x00040000 /* SCC2 Tx Clock Source is CLK11 */
893 #define CMXSCR_TS2CS_CLK12 0x00050000 /* SCC2 Tx Clock Source is CLK12 */
894 #define CMXSCR_TS2CS_CLK3 0x00060000 /* SCC2 Tx Clock Source is CLK3 */
895 #define CMXSCR_TS2CS_CLK4 0x00070000 /* SCC2 Tx Clock Source is CLK4 */
897 #define CMXSCR_RS3CS_BRG1 0x00000000 /* SCC3 Rx Clock Source is BRG1 */
898 #define CMXSCR_RS3CS_BRG2 0x00000800 /* SCC3 Rx Clock Source is BRG2 */
899 #define CMXSCR_RS3CS_BRG3 0x00001000 /* SCC3 Rx Clock Source is BRG3 */
900 #define CMXSCR_RS3CS_BRG4 0x00001800 /* SCC3 Rx Clock Source is BRG4 */
901 #define CMXSCR_RS3CS_CLK5 0x00002000 /* SCC3 Rx Clock Source is CLK5 */
902 #define CMXSCR_RS3CS_CLK6 0x00002800 /* SCC3 Rx Clock Source is CLK6 */
903 #define CMXSCR_RS3CS_CLK7 0x00003000 /* SCC3 Rx Clock Source is CLK7 */
904 #define CMXSCR_RS3CS_CLK8 0x00003800 /* SCC3 Rx Clock Source is CLK8 */
906 #define CMXSCR_TS3CS_BRG1 0x00000000 /* SCC3 Tx Clock Source is BRG1 */
907 #define CMXSCR_TS3CS_BRG2 0x00000100 /* SCC3 Tx Clock Source is BRG2 */
908 #define CMXSCR_TS3CS_BRG3 0x00000200 /* SCC3 Tx Clock Source is BRG3 */
909 #define CMXSCR_TS3CS_BRG4 0x00000300 /* SCC3 Tx Clock Source is BRG4 */
910 #define CMXSCR_TS3CS_CLK5 0x00000400 /* SCC3 Tx Clock Source is CLK5 */
911 #define CMXSCR_TS3CS_CLK6 0x00000500 /* SCC3 Tx Clock Source is CLK6 */
912 #define CMXSCR_TS3CS_CLK7 0x00000600 /* SCC3 Tx Clock Source is CLK7 */
913 #define CMXSCR_TS3CS_CLK8 0x00000700 /* SCC3 Tx Clock Source is CLK8 */
915 #define CMXSCR_RS4CS_BRG1 0x00000000 /* SCC4 Rx Clock Source is BRG1 */
916 #define CMXSCR_RS4CS_BRG2 0x00000008 /* SCC4 Rx Clock Source is BRG2 */
917 #define CMXSCR_RS4CS_BRG3 0x00000010 /* SCC4 Rx Clock Source is BRG3 */
918 #define CMXSCR_RS4CS_BRG4 0x00000018 /* SCC4 Rx Clock Source is BRG4 */
919 #define CMXSCR_RS4CS_CLK5 0x00000020 /* SCC4 Rx Clock Source is CLK5 */
920 #define CMXSCR_RS4CS_CLK6 0x00000028 /* SCC4 Rx Clock Source is CLK6 */
921 #define CMXSCR_RS4CS_CLK7 0x00000030 /* SCC4 Rx Clock Source is CLK7 */
922 #define CMXSCR_RS4CS_CLK8 0x00000038 /* SCC4 Rx Clock Source is CLK8 */
924 #define CMXSCR_TS4CS_BRG1 0x00000000 /* SCC4 Tx Clock Source is BRG1 */
925 #define CMXSCR_TS4CS_BRG2 0x00000001 /* SCC4 Tx Clock Source is BRG2 */
926 #define CMXSCR_TS4CS_BRG3 0x00000002 /* SCC4 Tx Clock Source is BRG3 */
927 #define CMXSCR_TS4CS_BRG4 0x00000003 /* SCC4 Tx Clock Source is BRG4 */
928 #define CMXSCR_TS4CS_CLK5 0x00000004 /* SCC4 Tx Clock Source is CLK5 */
929 #define CMXSCR_TS4CS_CLK6 0x00000005 /* SCC4 Tx Clock Source is CLK6 */
930 #define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */
931 #define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */
933 /*-----------------------------------------------------------------------
934 * SIUMCR - SIU Module Configuration Register 4-31
941 #define SIUMCR_DPPC01 0x04000000 /* - " - */
942 #define SIUMCR_DPPC10 0x08000000 /* - " - */
943 #define SIUMCR_DPPC11 0x0c000000 /* - " - */
945 #define SIUMCR_L2CPC01 0x01000000 /* - " - */
946 #define SIUMCR_L2CPC10 0x02000000 /* - " - */
947 #define SIUMCR_L2CPC11 0x03000000 /* - " - */
949 #define SIUMCR_LBPC01 0x00400000 /* - " - */
950 #define SIUMCR_LBPC10 0x00800000 /* - " - */
951 #define SIUMCR_LBPC11 0x00c00000 /* - " - */
953 #define SIUMCR_APPC01 0x00100000 /* - " - */
954 #define SIUMCR_APPC10 0x00200000 /* - " - */
955 #define SIUMCR_APPC11 0x00300000 /* - " - */
957 #define SIUMCR_CS10PC01 0x00040000 /* - " - */
958 #define SIUMCR_CS10PC10 0x00080000 /* - " - */
959 #define SIUMCR_CS10PC11 0x000c0000 /* - " - */
961 #define SIUMCR_BCTLC01 0x00010000 /* - " - */
962 #define SIUMCR_BCTLC10 0x00020000 /* - " - */
963 #define SIUMCR_BCTLC11 0x00030000 /* - " - */
965 #define SIUMCR_MMR01 0x00004000 /* - " - */
966 #define SIUMCR_MMR10 0x00008000 /* - " - */
967 #define SIUMCR_MMR11 0x0000c000 /* - " - */
970 /*-----------------------------------------------------------------------
971 * SCCR - System Clock Control Register 9-8
984 /* FCC iop & clock configuration. BSP code is responsible to define Fx_RXCLK & Fx_TXCLK
985 * in order to use clock-computing stuff below for the FCC x
989 #define PC_CLK(x) ((uint)(1<<(x-1))) /* FCC CLK I/O ports */
991 #define CMXFCR_RF1CS(x) ((uint)((x-5)<<27)) /* FCC1 Receive Clock Source */
992 #define CMXFCR_TF1CS(x) ((uint)((x-5)<<24)) /* FCC1 Transmit Clock Source */
993 #define CMXFCR_RF2CS(x) ((uint)((x-9)<<19)) /* FCC2 Receive Clock Source */
994 #define CMXFCR_TF2CS(x) ((uint)((x-9)<<16)) /* FCC2 Transmit Clock Source */
995 #define CMXFCR_RF3CS(x) ((uint)((x-9)<<11)) /* FCC3 Receive Clock Source */
996 #define CMXFCR_TF3CS(x) ((uint)((x-9)<<8)) /* FCC3 Transmit Clock Source */
1112 CPM_CLK1, /* Clock 1 */
1113 CPM_CLK2, /* Clock 2 */
1114 CPM_CLK3, /* Clock 3 */
1115 CPM_CLK4, /* Clock 4 */
1116 CPM_CLK5, /* Clock 5 */
1117 CPM_CLK6, /* Clock 6 */
1118 CPM_CLK7, /* Clock 7 */
1119 CPM_CLK8, /* Clock 8 */
1120 CPM_CLK9, /* Clock 9 */
1121 CPM_CLK10, /* Clock 10 */
1122 CPM_CLK11, /* Clock 11 */
1123 CPM_CLK12, /* Clock 12 */
1124 CPM_CLK13, /* Clock 13 */
1125 CPM_CLK14, /* Clock 14 */
1126 CPM_CLK15, /* Clock 15 */
1127 CPM_CLK16, /* Clock 16 */
1128 CPM_CLK17, /* Clock 17 */
1129 CPM_CLK18, /* Clock 18 */
1130 CPM_CLK19, /* Clock 19 */
1131 CPM_CLK20, /* Clock 20 */
1135 int __init cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode);
1136 int __init cpm2_smc_clk_setup(enum cpm_clk_target target, int clock);