Lines Matching +full:0 +full:x00280000
20 #define CPM_CR_RST ((uint)0x80000000)
21 #define CPM_CR_PAGE ((uint)0x7c000000)
22 #define CPM_CR_SBLOCK ((uint)0x03e00000)
23 #define CPM_CR_FLG ((uint)0x00010000)
24 #define CPM_CR_MCN ((uint)0x00003fc0)
25 #define CPM_CR_OPCODE ((uint)0x0000000f)
29 #define CPM_CR_SCC1_SBLOCK (0x04)
30 #define CPM_CR_SCC2_SBLOCK (0x05)
31 #define CPM_CR_SCC3_SBLOCK (0x06)
32 #define CPM_CR_SCC4_SBLOCK (0x07)
33 #define CPM_CR_SMC1_SBLOCK (0x08)
34 #define CPM_CR_SMC2_SBLOCK (0x09)
35 #define CPM_CR_SPI_SBLOCK (0x0a)
36 #define CPM_CR_I2C_SBLOCK (0x0b)
37 #define CPM_CR_TIMER_SBLOCK (0x0f)
38 #define CPM_CR_RAND_SBLOCK (0x0e)
39 #define CPM_CR_FCC1_SBLOCK (0x10)
40 #define CPM_CR_FCC2_SBLOCK (0x11)
41 #define CPM_CR_FCC3_SBLOCK (0x12)
42 #define CPM_CR_IDMA1_SBLOCK (0x14)
43 #define CPM_CR_IDMA2_SBLOCK (0x15)
44 #define CPM_CR_IDMA3_SBLOCK (0x16)
45 #define CPM_CR_IDMA4_SBLOCK (0x17)
46 #define CPM_CR_MCC1_SBLOCK (0x1c)
48 #define CPM_CR_FCC_SBLOCK(x) (x + 0x10)
50 #define CPM_CR_SCC1_PAGE (0x00)
51 #define CPM_CR_SCC2_PAGE (0x01)
52 #define CPM_CR_SCC3_PAGE (0x02)
53 #define CPM_CR_SCC4_PAGE (0x03)
54 #define CPM_CR_SMC1_PAGE (0x07)
55 #define CPM_CR_SMC2_PAGE (0x08)
56 #define CPM_CR_SPI_PAGE (0x09)
57 #define CPM_CR_I2C_PAGE (0x0a)
58 #define CPM_CR_TIMER_PAGE (0x0a)
59 #define CPM_CR_RAND_PAGE (0x0a)
60 #define CPM_CR_FCC1_PAGE (0x04)
61 #define CPM_CR_FCC2_PAGE (0x05)
62 #define CPM_CR_FCC3_PAGE (0x06)
63 #define CPM_CR_IDMA1_PAGE (0x07)
64 #define CPM_CR_IDMA2_PAGE (0x08)
65 #define CPM_CR_IDMA3_PAGE (0x09)
66 #define CPM_CR_IDMA4_PAGE (0x0a)
67 #define CPM_CR_MCC1_PAGE (0x07)
68 #define CPM_CR_MCC2_PAGE (0x08)
70 #define CPM_CR_FCC_PAGE(x) (x + 0x04)
74 #define CPM_CR_START_IDMA ((ushort)0x0009)
94 #define CPM_BRG_RST ((uint)0x00020000)
95 #define CPM_BRG_EN ((uint)0x00010000)
96 #define CPM_BRG_EXTC_INT ((uint)0x00000000)
97 #define CPM_BRG_EXTC_CLK3_9 ((uint)0x00004000)
98 #define CPM_BRG_EXTC_CLK5_15 ((uint)0x00008000)
99 #define CPM_BRG_ATB ((uint)0x00002000)
100 #define CPM_BRG_CD_MASK ((uint)0x00001ffe)
101 #define CPM_BRG_DIV16 ((uint)0x00000001)
113 __cpm2_setbrg(brg, rate, CPM2_BRG_UART_CLK, 0, CPM_BRG_EXTC_INT); in cpm_setbrg()
126 #define PROFF_SCC1 ((uint)0x8000)
127 #define PROFF_SCC2 ((uint)0x8100)
128 #define PROFF_SCC3 ((uint)0x8200)
129 #define PROFF_SCC4 ((uint)0x8300)
130 #define PROFF_FCC1 ((uint)0x8400)
131 #define PROFF_FCC2 ((uint)0x8500)
132 #define PROFF_FCC3 ((uint)0x8600)
133 #define PROFF_MCC1 ((uint)0x8700)
134 #define PROFF_SMC1_BASE ((uint)0x87fc)
135 #define PROFF_IDMA1_BASE ((uint)0x87fe)
136 #define PROFF_MCC2 ((uint)0x8800)
137 #define PROFF_SMC2_BASE ((uint)0x88fc)
138 #define PROFF_IDMA2_BASE ((uint)0x88fe)
139 #define PROFF_SPI_BASE ((uint)0x89fc)
140 #define PROFF_IDMA3_BASE ((uint)0x89fe)
141 #define PROFF_TIMERS ((uint)0x8ae0)
142 #define PROFF_REVNUM ((uint)0x8af0)
143 #define PROFF_RAND ((uint)0x8af8)
144 #define PROFF_I2C_BASE ((uint)0x8afc)
145 #define PROFF_IDMA4_BASE ((uint)0x8afe)
147 #define PROFF_SCC_SIZE ((uint)0x100)
148 #define PROFF_FCC_SIZE ((uint)0x100)
157 #define PROFF_SMC1 (0)
190 #define SMCMR_REN ((ushort)0x0001)
191 #define SMCMR_TEN ((ushort)0x0002)
192 #define SMCMR_DM ((ushort)0x000c)
193 #define SMCMR_SM_GCI ((ushort)0x0000)
194 #define SMCMR_SM_UART ((ushort)0x0020)
195 #define SMCMR_SM_TRANS ((ushort)0x0030)
196 #define SMCMR_SM_MASK ((ushort)0x0030)
197 #define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
199 #define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
201 #define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
202 #define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
207 #define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */
208 #define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */
209 #define SMCM_TXE ((unsigned char)0x10)
210 #define SMCM_BSY ((unsigned char)0x04)
211 #define SMCM_TX ((unsigned char)0x02)
212 #define SMCM_RX ((unsigned char)0x01)
216 #define SCC_GSMRH_IRP ((uint)0x00040000)
217 #define SCC_GSMRH_GDE ((uint)0x00010000)
218 #define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
219 #define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
220 #define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
221 #define SCC_GSMRH_REVD ((uint)0x00002000)
222 #define SCC_GSMRH_TRX ((uint)0x00001000)
223 #define SCC_GSMRH_TTX ((uint)0x00000800)
224 #define SCC_GSMRH_CDP ((uint)0x00000400)
225 #define SCC_GSMRH_CTSP ((uint)0x00000200)
226 #define SCC_GSMRH_CDS ((uint)0x00000100)
227 #define SCC_GSMRH_CTSS ((uint)0x00000080)
228 #define SCC_GSMRH_TFL ((uint)0x00000040)
229 #define SCC_GSMRH_RFW ((uint)0x00000020)
230 #define SCC_GSMRH_TXSY ((uint)0x00000010)
231 #define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
232 #define SCC_GSMRH_SYNL8 ((uint)0x00000008)
233 #define SCC_GSMRH_SYNL4 ((uint)0x00000004)
234 #define SCC_GSMRH_RTSM ((uint)0x00000002)
235 #define SCC_GSMRH_RSYN ((uint)0x00000001)
237 #define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
238 #define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
239 #define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
240 #define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
241 #define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
242 #define SCC_GSMRL_TCI ((uint)0x10000000)
243 #define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
244 #define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
245 #define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
246 #define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
247 #define SCC_GSMRL_RINV ((uint)0x02000000)
248 #define SCC_GSMRL_TINV ((uint)0x01000000)
249 #define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
250 #define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
251 #define SCC_GSMRL_TPL_48 ((uint)0x00800000)
252 #define SCC_GSMRL_TPL_32 ((uint)0x00600000)
253 #define SCC_GSMRL_TPL_16 ((uint)0x00400000)
254 #define SCC_GSMRL_TPL_8 ((uint)0x00200000)
255 #define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
256 #define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
257 #define SCC_GSMRL_TPP_01 ((uint)0x00100000)
258 #define SCC_GSMRL_TPP_10 ((uint)0x00080000)
259 #define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
260 #define SCC_GSMRL_TEND ((uint)0x00040000)
261 #define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
262 #define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
263 #define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
264 #define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
265 #define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
266 #define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
267 #define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
268 #define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
269 #define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
270 #define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
271 #define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
272 #define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
273 #define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
274 #define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
275 #define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
276 #define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
277 #define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
278 #define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
279 #define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
280 #define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
281 #define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
282 #define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
283 #define SCC_GSMRL_ENR ((uint)0x00000020)
284 #define SCC_GSMRL_ENT ((uint)0x00000010)
285 #define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
286 #define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
287 #define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
288 #define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
289 #define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
290 #define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
291 #define SCC_GSMRL_MODE_UART ((uint)0x00000004)
292 #define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
293 #define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
294 #define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
296 #define SCC_TODR_TOD ((ushort)0x8000)
300 #define SCCM_TXE ((unsigned char)0x10)
301 #define SCCM_BSY ((unsigned char)0x04)
302 #define SCCM_TX ((unsigned char)0x02)
303 #define SCCM_RX ((unsigned char)0x01)
327 #define SCC_EB ((u_char) 0x10) /* Set big endian byte order */
328 #define SCC_GBL ((u_char) 0x20) /* Snooping enabled */
353 uint sen_tbuf0data0; /* Save area 0 - current frame */
365 uint sen_tbuf1data0; /* Save area 0 - current frame */
388 #define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
389 #define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
390 #define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
391 #define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
392 #define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
393 #define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
397 #define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
398 #define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
399 #define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
400 #define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
401 #define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
402 #define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
403 #define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
404 #define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
405 #define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
406 #define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
407 #define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
408 #define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
409 #define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
444 #define UART_SCCM_GLR ((ushort)0x1000)
445 #define UART_SCCM_GLT ((ushort)0x0800)
446 #define UART_SCCM_AB ((ushort)0x0200)
447 #define UART_SCCM_IDL ((ushort)0x0100)
448 #define UART_SCCM_GRA ((ushort)0x0080)
449 #define UART_SCCM_BRKE ((ushort)0x0040)
450 #define UART_SCCM_BRKS ((ushort)0x0020)
451 #define UART_SCCM_CCR ((ushort)0x0008)
452 #define UART_SCCM_BSY ((ushort)0x0004)
453 #define UART_SCCM_TX ((ushort)0x0002)
454 #define UART_SCCM_RX ((ushort)0x0001)
458 #define SCU_PSMR_FLC ((ushort)0x8000)
459 #define SCU_PSMR_SL ((ushort)0x4000)
460 #define SCU_PSMR_CL ((ushort)0x3000)
461 #define SCU_PSMR_UM ((ushort)0x0c00)
462 #define SCU_PSMR_FRZ ((ushort)0x0200)
463 #define SCU_PSMR_RZS ((ushort)0x0100)
464 #define SCU_PSMR_SYN ((ushort)0x0080)
465 #define SCU_PSMR_DRT ((ushort)0x0040)
466 #define SCU_PSMR_PEN ((ushort)0x0010)
467 #define SCU_PSMR_RPM ((ushort)0x000c)
468 #define SCU_PSMR_REVP ((ushort)0x0008)
469 #define SCU_PSMR_TPM ((ushort)0x0003)
470 #define SCU_PSMR_TEVP ((ushort)0x0002)
482 #define FCC_GFMR_DIAG_NORM ((uint)0x00000000)
483 #define FCC_GFMR_DIAG_LE ((uint)0x40000000)
484 #define FCC_GFMR_DIAG_AE ((uint)0x80000000)
485 #define FCC_GFMR_DIAG_ALE ((uint)0xc0000000)
486 #define FCC_GFMR_TCI ((uint)0x20000000)
487 #define FCC_GFMR_TRX ((uint)0x10000000)
488 #define FCC_GFMR_TTX ((uint)0x08000000)
489 #define FCC_GFMR_CDP ((uint)0x04000000)
490 #define FCC_GFMR_CTSP ((uint)0x02000000)
491 #define FCC_GFMR_CDS ((uint)0x01000000)
492 #define FCC_GFMR_CTSS ((uint)0x00800000)
493 #define FCC_GFMR_SYNL_NONE ((uint)0x00000000)
494 #define FCC_GFMR_SYNL_AUTO ((uint)0x00004000)
495 #define FCC_GFMR_SYNL_8 ((uint)0x00008000)
496 #define FCC_GFMR_SYNL_16 ((uint)0x0000c000)
497 #define FCC_GFMR_RTSM ((uint)0x00002000)
498 #define FCC_GFMR_RENC_NRZ ((uint)0x00000000)
499 #define FCC_GFMR_RENC_NRZI ((uint)0x00000800)
500 #define FCC_GFMR_REVD ((uint)0x00000400)
501 #define FCC_GFMR_TENC_NRZ ((uint)0x00000000)
502 #define FCC_GFMR_TENC_NRZI ((uint)0x00000100)
503 #define FCC_GFMR_TCRC_16 ((uint)0x00000000)
504 #define FCC_GFMR_TCRC_32 ((uint)0x00000080)
505 #define FCC_GFMR_ENR ((uint)0x00000020)
506 #define FCC_GFMR_ENT ((uint)0x00000010)
507 #define FCC_GFMR_MODE_ENET ((uint)0x0000000c)
508 #define FCC_GFMR_MODE_ATM ((uint)0x0000000a)
509 #define FCC_GFMR_MODE_HDLC ((uint)0x00000000)
600 #define FCC_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
601 #define FCC_ENET_RXC ((ushort)0x0040) /* Control Frame Received */
602 #define FCC_ENET_TXC ((ushort)0x0020) /* Out of seq. Tx sent */
603 #define FCC_ENET_TXE ((ushort)0x0010) /* Transmit Error */
604 #define FCC_ENET_RXF ((ushort)0x0008) /* Full frame received */
605 #define FCC_ENET_BSY ((ushort)0x0004) /* Busy. Rx Frame dropped */
606 #define FCC_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
607 #define FCC_ENET_RXB ((ushort)0x0001) /* A buffer was received */
611 #define FCC_PSMR_HBC ((uint)0x80000000) /* Enable heartbeat */
612 #define FCC_PSMR_FC ((uint)0x40000000) /* Force Collision */
613 #define FCC_PSMR_SBT ((uint)0x20000000) /* Stop backoff timer */
614 #define FCC_PSMR_LPB ((uint)0x10000000) /* Local protect. 1 = FDX */
615 #define FCC_PSMR_LCW ((uint)0x08000000) /* Late collision select */
616 #define FCC_PSMR_FDE ((uint)0x04000000) /* Full Duplex Enable */
617 #define FCC_PSMR_MON ((uint)0x02000000) /* RMON Enable */
618 #define FCC_PSMR_PRO ((uint)0x00400000) /* Promiscuous Enable */
619 #define FCC_PSMR_FCE ((uint)0x00200000) /* Flow Control Enable */
620 #define FCC_PSMR_RSH ((uint)0x00100000) /* Receive Short Frames */
621 #define FCC_PSMR_CAM ((uint)0x00000400) /* CAM enable */
622 #define FCC_PSMR_BRO ((uint)0x00000200) /* Broadcast pkt discard */
623 #define FCC_PSMR_ENCRC ((uint)0x00000080) /* Use 32-bit CRC */
671 #define IDMA_DCM_FB ((ushort)0x8000) /* fly-by mode */
672 #define IDMA_DCM_LP ((ushort)0x4000) /* low priority */
673 #define IDMA_DCM_TC2 ((ushort)0x0400) /* value driven on TC[2] */
674 #define IDMA_DCM_DMA_WRAP_MASK ((ushort)0x01c0) /* mask for DMA wrap */
675 #define IDMA_DCM_DMA_WRAP_64 ((ushort)0x0000) /* 64-byte DMA xfer buffer */
676 #define IDMA_DCM_DMA_WRAP_128 ((ushort)0x0040) /* 128-byte DMA xfer buffer */
677 #define IDMA_DCM_DMA_WRAP_256 ((ushort)0x0080) /* 256-byte DMA xfer buffer */
678 #define IDMA_DCM_DMA_WRAP_512 ((ushort)0x00c0) /* 512-byte DMA xfer buffer */
679 #define IDMA_DCM_DMA_WRAP_1024 ((ushort)0x0100) /* 1024-byte DMA xfer buffer */
680 #define IDMA_DCM_DMA_WRAP_2048 ((ushort)0x0140) /* 2048-byte DMA xfer buffer */
681 #define IDMA_DCM_SINC ((ushort)0x0020) /* source inc addr */
682 #define IDMA_DCM_DINC ((ushort)0x0010) /* destination inc addr */
683 #define IDMA_DCM_ERM ((ushort)0x0008) /* external request mode */
684 #define IDMA_DCM_DT ((ushort)0x0004) /* DONE treatment */
685 #define IDMA_DCM_SD_MASK ((ushort)0x0003) /* mask for SD bit field */
686 #define IDMA_DCM_SD_MEM2MEM ((ushort)0x0000) /* memory-to-memory xfer */
687 #define IDMA_DCM_SD_PER2MEM ((ushort)0x0002) /* peripheral-to-memory xfer */
688 #define IDMA_DCM_SD_MEM2PER ((ushort)0x0001) /* memory-to-peripheral xfer */
701 #define IDMA_BD_V ((uint)0x80000000) /* valid */
702 #define IDMA_BD_W ((uint)0x20000000) /* wrap */
703 #define IDMA_BD_I ((uint)0x10000000) /* interrupt */
704 #define IDMA_BD_L ((uint)0x08000000) /* last */
705 #define IDMA_BD_CM ((uint)0x02000000) /* continuous mode */
706 #define IDMA_BD_SDN ((uint)0x00400000) /* source done */
707 #define IDMA_BD_DDN ((uint)0x00200000) /* destination done */
708 #define IDMA_BD_DGBL ((uint)0x00100000) /* destination global */
709 #define IDMA_BD_DBO_LE ((uint)0x00040000) /* little-end dest byte order */
710 #define IDMA_BD_DBO_BE ((uint)0x00080000) /* big-end dest byte order */
711 #define IDMA_BD_DDTB ((uint)0x00010000) /* destination data bus */
712 #define IDMA_BD_SGBL ((uint)0x00002000) /* source global */
713 #define IDMA_BD_SBO_LE ((uint)0x00000800) /* little-end src byte order */
714 #define IDMA_BD_SBO_BE ((uint)0x00001000) /* big-end src byte order */
715 #define IDMA_BD_SDTB ((uint)0x00000200) /* source data bus */
728 #define IDMA_EVENT_SC ((unsigned char)0x08) /* stop completed */
729 #define IDMA_EVENT_OB ((unsigned char)0x04) /* out of buffers */
730 #define IDMA_EVENT_EDN ((unsigned char)0x02) /* external DONE asserted */
731 #define IDMA_EVENT_BC ((unsigned char)0x01) /* buffer descriptor complete */
735 #define RCCR_TIME ((uint)0x80000000) /* timer enable */
736 #define RCCR_TIMEP_MASK ((uint)0x3f000000) /* mask for timer period bit field */
737 #define RCCR_DR0M ((uint)0x00800000) /* IDMA0 request mode */
738 #define RCCR_DR1M ((uint)0x00400000) /* IDMA1 request mode */
739 #define RCCR_DR2M ((uint)0x00000080) /* IDMA2 request mode */
740 #define RCCR_DR3M ((uint)0x00000040) /* IDMA3 request mode */
741 #define RCCR_DR0QP_MASK ((uint)0x00300000) /* mask for IDMA0 req priority */
742 #define RCCR_DR0QP_HIGH ((uint)0x00000000) /* IDMA0 has high req priority */
743 #define RCCR_DR0QP_MED ((uint)0x00100000) /* IDMA0 has medium req priority */
744 #define RCCR_DR0QP_LOW ((uint)0x00200000) /* IDMA0 has low req priority */
745 #define RCCR_DR1QP_MASK ((uint)0x00030000) /* mask for IDMA1 req priority */
746 #define RCCR_DR1QP_HIGH ((uint)0x00000000) /* IDMA1 has high req priority */
747 #define RCCR_DR1QP_MED ((uint)0x00010000) /* IDMA1 has medium req priority */
748 #define RCCR_DR1QP_LOW ((uint)0x00020000) /* IDMA1 has low req priority */
749 #define RCCR_DR2QP_MASK ((uint)0x00000030) /* mask for IDMA2 req priority */
750 #define RCCR_DR2QP_HIGH ((uint)0x00000000) /* IDMA2 has high req priority */
751 #define RCCR_DR2QP_MED ((uint)0x00000010) /* IDMA2 has medium req priority */
752 #define RCCR_DR2QP_LOW ((uint)0x00000020) /* IDMA2 has low req priority */
753 #define RCCR_DR3QP_MASK ((uint)0x00000003) /* mask for IDMA3 req priority */
754 #define RCCR_DR3QP_HIGH ((uint)0x00000000) /* IDMA3 has high req priority */
755 #define RCCR_DR3QP_MED ((uint)0x00000001) /* IDMA3 has medium req priority */
756 #define RCCR_DR3QP_LOW ((uint)0x00000002) /* IDMA3 has low req priority */
757 #define RCCR_EIE ((uint)0x00080000) /* external interrupt enable */
758 #define RCCR_SCD ((uint)0x00040000) /* scheduler configuration */
759 #define RCCR_ERAM_MASK ((uint)0x0000e000) /* mask for enable RAM microcode */
760 #define RCCR_ERAM_0KB ((uint)0x00000000) /* use 0KB of dpram for microcode */
761 #define RCCR_ERAM_2KB ((uint)0x00002000) /* use 2KB of dpram for microcode */
762 #define RCCR_ERAM_4KB ((uint)0x00004000) /* use 4KB of dpram for microcode */
763 #define RCCR_ERAM_6KB ((uint)0x00006000) /* use 6KB of dpram for microcode */
764 #define RCCR_ERAM_8KB ((uint)0x00008000) /* use 8KB of dpram for microcode */
765 #define RCCR_ERAM_10KB ((uint)0x0000a000) /* use 10KB of dpram for microcode */
766 #define RCCR_ERAM_12KB ((uint)0x0000c000) /* use 12KB of dpram for microcode */
767 #define RCCR_EDM0 ((uint)0x00000800) /* DREQ0 edge detect mode */
768 #define RCCR_EDM1 ((uint)0x00000400) /* DREQ1 edge detect mode */
769 #define RCCR_EDM2 ((uint)0x00000200) /* DREQ2 edge detect mode */
770 #define RCCR_EDM3 ((uint)0x00000100) /* DREQ3 edge detect mode */
771 #define RCCR_DEM01 ((uint)0x00000008) /* DONE0/DONE1 edge detect mode */
772 #define RCCR_DEM23 ((uint)0x00000004) /* DONE2/DONE3 edge detect mode */
777 #define CMXFCR_FC1 0x40000000 /* FCC1 connection */
778 #define CMXFCR_RF1CS_MSK 0x38000000 /* Receive FCC1 Clock Source Mask */
779 #define CMXFCR_TF1CS_MSK 0x07000000 /* Transmit FCC1 Clock Source Mask */
780 #define CMXFCR_FC2 0x00400000 /* FCC2 connection */
781 #define CMXFCR_RF2CS_MSK 0x00380000 /* Receive FCC2 Clock Source Mask */
782 #define CMXFCR_TF2CS_MSK 0x00070000 /* Transmit FCC2 Clock Source Mask */
783 #define CMXFCR_FC3 0x00004000 /* FCC3 connection */
784 #define CMXFCR_RF3CS_MSK 0x00003800 /* Receive FCC3 Clock Source Mask */
785 #define CMXFCR_TF3CS_MSK 0x00000700 /* Transmit FCC3 Clock Source Mask */
787 #define CMXFCR_RF1CS_BRG5 0x00000000 /* Receive FCC1 Clock Source is BRG5 */
788 #define CMXFCR_RF1CS_BRG6 0x08000000 /* Receive FCC1 Clock Source is BRG6 */
789 #define CMXFCR_RF1CS_BRG7 0x10000000 /* Receive FCC1 Clock Source is BRG7 */
790 #define CMXFCR_RF1CS_BRG8 0x18000000 /* Receive FCC1 Clock Source is BRG8 */
791 #define CMXFCR_RF1CS_CLK9 0x20000000 /* Receive FCC1 Clock Source is CLK9 */
792 #define CMXFCR_RF1CS_CLK10 0x28000000 /* Receive FCC1 Clock Source is CLK10 */
793 #define CMXFCR_RF1CS_CLK11 0x30000000 /* Receive FCC1 Clock Source is CLK11 */
794 #define CMXFCR_RF1CS_CLK12 0x38000000 /* Receive FCC1 Clock Source is CLK12 */
796 #define CMXFCR_TF1CS_BRG5 0x00000000 /* Transmit FCC1 Clock Source is BRG5 */
797 #define CMXFCR_TF1CS_BRG6 0x01000000 /* Transmit FCC1 Clock Source is BRG6 */
798 #define CMXFCR_TF1CS_BRG7 0x02000000 /* Transmit FCC1 Clock Source is BRG7 */
799 #define CMXFCR_TF1CS_BRG8 0x03000000 /* Transmit FCC1 Clock Source is BRG8 */
800 #define CMXFCR_TF1CS_CLK9 0x04000000 /* Transmit FCC1 Clock Source is CLK9 */
801 #define CMXFCR_TF1CS_CLK10 0x05000000 /* Transmit FCC1 Clock Source is CLK10 */
802 #define CMXFCR_TF1CS_CLK11 0x06000000 /* Transmit FCC1 Clock Source is CLK11 */
803 #define CMXFCR_TF1CS_CLK12 0x07000000 /* Transmit FCC1 Clock Source is CLK12 */
805 #define CMXFCR_RF2CS_BRG5 0x00000000 /* Receive FCC2 Clock Source is BRG5 */
806 #define CMXFCR_RF2CS_BRG6 0x00080000 /* Receive FCC2 Clock Source is BRG6 */
807 #define CMXFCR_RF2CS_BRG7 0x00100000 /* Receive FCC2 Clock Source is BRG7 */
808 #define CMXFCR_RF2CS_BRG8 0x00180000 /* Receive FCC2 Clock Source is BRG8 */
809 #define CMXFCR_RF2CS_CLK13 0x00200000 /* Receive FCC2 Clock Source is CLK13 */
810 #define CMXFCR_RF2CS_CLK14 0x00280000 /* Receive FCC2 Clock Source is CLK14 */
811 #define CMXFCR_RF2CS_CLK15 0x00300000 /* Receive FCC2 Clock Source is CLK15 */
812 #define CMXFCR_RF2CS_CLK16 0x00380000 /* Receive FCC2 Clock Source is CLK16 */
814 #define CMXFCR_TF2CS_BRG5 0x00000000 /* Transmit FCC2 Clock Source is BRG5 */
815 #define CMXFCR_TF2CS_BRG6 0x00010000 /* Transmit FCC2 Clock Source is BRG6 */
816 #define CMXFCR_TF2CS_BRG7 0x00020000 /* Transmit FCC2 Clock Source is BRG7 */
817 #define CMXFCR_TF2CS_BRG8 0x00030000 /* Transmit FCC2 Clock Source is BRG8 */
818 #define CMXFCR_TF2CS_CLK13 0x00040000 /* Transmit FCC2 Clock Source is CLK13 */
819 #define CMXFCR_TF2CS_CLK14 0x00050000 /* Transmit FCC2 Clock Source is CLK14 */
820 #define CMXFCR_TF2CS_CLK15 0x00060000 /* Transmit FCC2 Clock Source is CLK15 */
821 #define CMXFCR_TF2CS_CLK16 0x00070000 /* Transmit FCC2 Clock Source is CLK16 */
823 #define CMXFCR_RF3CS_BRG5 0x00000000 /* Receive FCC3 Clock Source is BRG5 */
824 #define CMXFCR_RF3CS_BRG6 0x00000800 /* Receive FCC3 Clock Source is BRG6 */
825 #define CMXFCR_RF3CS_BRG7 0x00001000 /* Receive FCC3 Clock Source is BRG7 */
826 #define CMXFCR_RF3CS_BRG8 0x00001800 /* Receive FCC3 Clock Source is BRG8 */
827 #define CMXFCR_RF3CS_CLK13 0x00002000 /* Receive FCC3 Clock Source is CLK13 */
828 #define CMXFCR_RF3CS_CLK14 0x00002800 /* Receive FCC3 Clock Source is CLK14 */
829 #define CMXFCR_RF3CS_CLK15 0x00003000 /* Receive FCC3 Clock Source is CLK15 */
830 #define CMXFCR_RF3CS_CLK16 0x00003800 /* Receive FCC3 Clock Source is CLK16 */
832 #define CMXFCR_TF3CS_BRG5 0x00000000 /* Transmit FCC3 Clock Source is BRG5 */
833 #define CMXFCR_TF3CS_BRG6 0x00000100 /* Transmit FCC3 Clock Source is BRG6 */
834 #define CMXFCR_TF3CS_BRG7 0x00000200 /* Transmit FCC3 Clock Source is BRG7 */
835 #define CMXFCR_TF3CS_BRG8 0x00000300 /* Transmit FCC3 Clock Source is BRG8 */
836 #define CMXFCR_TF3CS_CLK13 0x00000400 /* Transmit FCC3 Clock Source is CLK13 */
837 #define CMXFCR_TF3CS_CLK14 0x00000500 /* Transmit FCC3 Clock Source is CLK14 */
838 #define CMXFCR_TF3CS_CLK15 0x00000600 /* Transmit FCC3 Clock Source is CLK15 */
839 #define CMXFCR_TF3CS_CLK16 0x00000700 /* Transmit FCC3 Clock Source is CLK16 */
844 #define CMXSCR_GR1 0x80000000 /* Grant Support of SCC1 */
845 #define CMXSCR_SC1 0x40000000 /* SCC1 connection */
846 #define CMXSCR_RS1CS_MSK 0x38000000 /* Receive SCC1 Clock Source Mask */
847 #define CMXSCR_TS1CS_MSK 0x07000000 /* Transmit SCC1 Clock Source Mask */
848 #define CMXSCR_GR2 0x00800000 /* Grant Support of SCC2 */
849 #define CMXSCR_SC2 0x00400000 /* SCC2 connection */
850 #define CMXSCR_RS2CS_MSK 0x00380000 /* Receive SCC2 Clock Source Mask */
851 #define CMXSCR_TS2CS_MSK 0x00070000 /* Transmit SCC2 Clock Source Mask */
852 #define CMXSCR_GR3 0x00008000 /* Grant Support of SCC3 */
853 #define CMXSCR_SC3 0x00004000 /* SCC3 connection */
854 #define CMXSCR_RS3CS_MSK 0x00003800 /* Receive SCC3 Clock Source Mask */
855 #define CMXSCR_TS3CS_MSK 0x00000700 /* Transmit SCC3 Clock Source Mask */
856 #define CMXSCR_GR4 0x00000080 /* Grant Support of SCC4 */
857 #define CMXSCR_SC4 0x00000040 /* SCC4 connection */
858 #define CMXSCR_RS4CS_MSK 0x00000038 /* Receive SCC4 Clock Source Mask */
859 #define CMXSCR_TS4CS_MSK 0x00000007 /* Transmit SCC4 Clock Source Mask */
861 #define CMXSCR_RS1CS_BRG1 0x00000000 /* SCC1 Rx Clock Source is BRG1 */
862 #define CMXSCR_RS1CS_BRG2 0x08000000 /* SCC1 Rx Clock Source is BRG2 */
863 #define CMXSCR_RS1CS_BRG3 0x10000000 /* SCC1 Rx Clock Source is BRG3 */
864 #define CMXSCR_RS1CS_BRG4 0x18000000 /* SCC1 Rx Clock Source is BRG4 */
865 #define CMXSCR_RS1CS_CLK11 0x20000000 /* SCC1 Rx Clock Source is CLK11 */
866 #define CMXSCR_RS1CS_CLK12 0x28000000 /* SCC1 Rx Clock Source is CLK12 */
867 #define CMXSCR_RS1CS_CLK3 0x30000000 /* SCC1 Rx Clock Source is CLK3 */
868 #define CMXSCR_RS1CS_CLK4 0x38000000 /* SCC1 Rx Clock Source is CLK4 */
870 #define CMXSCR_TS1CS_BRG1 0x00000000 /* SCC1 Tx Clock Source is BRG1 */
871 #define CMXSCR_TS1CS_BRG2 0x01000000 /* SCC1 Tx Clock Source is BRG2 */
872 #define CMXSCR_TS1CS_BRG3 0x02000000 /* SCC1 Tx Clock Source is BRG3 */
873 #define CMXSCR_TS1CS_BRG4 0x03000000 /* SCC1 Tx Clock Source is BRG4 */
874 #define CMXSCR_TS1CS_CLK11 0x04000000 /* SCC1 Tx Clock Source is CLK11 */
875 #define CMXSCR_TS1CS_CLK12 0x05000000 /* SCC1 Tx Clock Source is CLK12 */
876 #define CMXSCR_TS1CS_CLK3 0x06000000 /* SCC1 Tx Clock Source is CLK3 */
877 #define CMXSCR_TS1CS_CLK4 0x07000000 /* SCC1 Tx Clock Source is CLK4 */
879 #define CMXSCR_RS2CS_BRG1 0x00000000 /* SCC2 Rx Clock Source is BRG1 */
880 #define CMXSCR_RS2CS_BRG2 0x00080000 /* SCC2 Rx Clock Source is BRG2 */
881 #define CMXSCR_RS2CS_BRG3 0x00100000 /* SCC2 Rx Clock Source is BRG3 */
882 #define CMXSCR_RS2CS_BRG4 0x00180000 /* SCC2 Rx Clock Source is BRG4 */
883 #define CMXSCR_RS2CS_CLK11 0x00200000 /* SCC2 Rx Clock Source is CLK11 */
884 #define CMXSCR_RS2CS_CLK12 0x00280000 /* SCC2 Rx Clock Source is CLK12 */
885 #define CMXSCR_RS2CS_CLK3 0x00300000 /* SCC2 Rx Clock Source is CLK3 */
886 #define CMXSCR_RS2CS_CLK4 0x00380000 /* SCC2 Rx Clock Source is CLK4 */
888 #define CMXSCR_TS2CS_BRG1 0x00000000 /* SCC2 Tx Clock Source is BRG1 */
889 #define CMXSCR_TS2CS_BRG2 0x00010000 /* SCC2 Tx Clock Source is BRG2 */
890 #define CMXSCR_TS2CS_BRG3 0x00020000 /* SCC2 Tx Clock Source is BRG3 */
891 #define CMXSCR_TS2CS_BRG4 0x00030000 /* SCC2 Tx Clock Source is BRG4 */
892 #define CMXSCR_TS2CS_CLK11 0x00040000 /* SCC2 Tx Clock Source is CLK11 */
893 #define CMXSCR_TS2CS_CLK12 0x00050000 /* SCC2 Tx Clock Source is CLK12 */
894 #define CMXSCR_TS2CS_CLK3 0x00060000 /* SCC2 Tx Clock Source is CLK3 */
895 #define CMXSCR_TS2CS_CLK4 0x00070000 /* SCC2 Tx Clock Source is CLK4 */
897 #define CMXSCR_RS3CS_BRG1 0x00000000 /* SCC3 Rx Clock Source is BRG1 */
898 #define CMXSCR_RS3CS_BRG2 0x00000800 /* SCC3 Rx Clock Source is BRG2 */
899 #define CMXSCR_RS3CS_BRG3 0x00001000 /* SCC3 Rx Clock Source is BRG3 */
900 #define CMXSCR_RS3CS_BRG4 0x00001800 /* SCC3 Rx Clock Source is BRG4 */
901 #define CMXSCR_RS3CS_CLK5 0x00002000 /* SCC3 Rx Clock Source is CLK5 */
902 #define CMXSCR_RS3CS_CLK6 0x00002800 /* SCC3 Rx Clock Source is CLK6 */
903 #define CMXSCR_RS3CS_CLK7 0x00003000 /* SCC3 Rx Clock Source is CLK7 */
904 #define CMXSCR_RS3CS_CLK8 0x00003800 /* SCC3 Rx Clock Source is CLK8 */
906 #define CMXSCR_TS3CS_BRG1 0x00000000 /* SCC3 Tx Clock Source is BRG1 */
907 #define CMXSCR_TS3CS_BRG2 0x00000100 /* SCC3 Tx Clock Source is BRG2 */
908 #define CMXSCR_TS3CS_BRG3 0x00000200 /* SCC3 Tx Clock Source is BRG3 */
909 #define CMXSCR_TS3CS_BRG4 0x00000300 /* SCC3 Tx Clock Source is BRG4 */
910 #define CMXSCR_TS3CS_CLK5 0x00000400 /* SCC3 Tx Clock Source is CLK5 */
911 #define CMXSCR_TS3CS_CLK6 0x00000500 /* SCC3 Tx Clock Source is CLK6 */
912 #define CMXSCR_TS3CS_CLK7 0x00000600 /* SCC3 Tx Clock Source is CLK7 */
913 #define CMXSCR_TS3CS_CLK8 0x00000700 /* SCC3 Tx Clock Source is CLK8 */
915 #define CMXSCR_RS4CS_BRG1 0x00000000 /* SCC4 Rx Clock Source is BRG1 */
916 #define CMXSCR_RS4CS_BRG2 0x00000008 /* SCC4 Rx Clock Source is BRG2 */
917 #define CMXSCR_RS4CS_BRG3 0x00000010 /* SCC4 Rx Clock Source is BRG3 */
918 #define CMXSCR_RS4CS_BRG4 0x00000018 /* SCC4 Rx Clock Source is BRG4 */
919 #define CMXSCR_RS4CS_CLK5 0x00000020 /* SCC4 Rx Clock Source is CLK5 */
920 #define CMXSCR_RS4CS_CLK6 0x00000028 /* SCC4 Rx Clock Source is CLK6 */
921 #define CMXSCR_RS4CS_CLK7 0x00000030 /* SCC4 Rx Clock Source is CLK7 */
922 #define CMXSCR_RS4CS_CLK8 0x00000038 /* SCC4 Rx Clock Source is CLK8 */
924 #define CMXSCR_TS4CS_BRG1 0x00000000 /* SCC4 Tx Clock Source is BRG1 */
925 #define CMXSCR_TS4CS_BRG2 0x00000001 /* SCC4 Tx Clock Source is BRG2 */
926 #define CMXSCR_TS4CS_BRG3 0x00000002 /* SCC4 Tx Clock Source is BRG3 */
927 #define CMXSCR_TS4CS_BRG4 0x00000003 /* SCC4 Tx Clock Source is BRG4 */
928 #define CMXSCR_TS4CS_CLK5 0x00000004 /* SCC4 Tx Clock Source is CLK5 */
929 #define CMXSCR_TS4CS_CLK6 0x00000005 /* SCC4 Tx Clock Source is CLK6 */
930 #define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */
931 #define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */
936 #define SIUMCR_BBD 0x80000000 /* Bus Busy Disable */
937 #define SIUMCR_ESE 0x40000000 /* External Snoop Enable */
938 #define SIUMCR_PBSE 0x20000000 /* Parity Byte Select Enable */
939 #define SIUMCR_CDIS 0x10000000 /* Core Disable */
940 #define SIUMCR_DPPC00 0x00000000 /* Data Parity Pins Configuration*/
941 #define SIUMCR_DPPC01 0x04000000 /* - " - */
942 #define SIUMCR_DPPC10 0x08000000 /* - " - */
943 #define SIUMCR_DPPC11 0x0c000000 /* - " - */
944 #define SIUMCR_L2CPC00 0x00000000 /* L2 Cache Pins Configuration */
945 #define SIUMCR_L2CPC01 0x01000000 /* - " - */
946 #define SIUMCR_L2CPC10 0x02000000 /* - " - */
947 #define SIUMCR_L2CPC11 0x03000000 /* - " - */
948 #define SIUMCR_LBPC00 0x00000000 /* Local Bus Pins Configuration */
949 #define SIUMCR_LBPC01 0x00400000 /* - " - */
950 #define SIUMCR_LBPC10 0x00800000 /* - " - */
951 #define SIUMCR_LBPC11 0x00c00000 /* - " - */
952 #define SIUMCR_APPC00 0x00000000 /* Address Parity Pins Configuration*/
953 #define SIUMCR_APPC01 0x00100000 /* - " - */
954 #define SIUMCR_APPC10 0x00200000 /* - " - */
955 #define SIUMCR_APPC11 0x00300000 /* - " - */
956 #define SIUMCR_CS10PC00 0x00000000 /* CS10 Pin Configuration */
957 #define SIUMCR_CS10PC01 0x00040000 /* - " - */
958 #define SIUMCR_CS10PC10 0x00080000 /* - " - */
959 #define SIUMCR_CS10PC11 0x000c0000 /* - " - */
960 #define SIUMCR_BCTLC00 0x00000000 /* Buffer Control Configuration */
961 #define SIUMCR_BCTLC01 0x00010000 /* - " - */
962 #define SIUMCR_BCTLC10 0x00020000 /* - " - */
963 #define SIUMCR_BCTLC11 0x00030000 /* - " - */
964 #define SIUMCR_MMR00 0x00000000 /* Mask Masters Requests */
965 #define SIUMCR_MMR01 0x00004000 /* - " - */
966 #define SIUMCR_MMR10 0x00008000 /* - " - */
967 #define SIUMCR_MMR11 0x0000c000 /* - " - */
968 #define SIUMCR_LPBSE 0x00002000 /* LocalBus Parity Byte Select Enable*/
973 #define SCCR_PCI_MODE 0x00000100 /* PCI Mode */
974 #define SCCR_PCI_MODCK 0x00000080 /* Value of PCI_MODCK pin */
975 #define SCCR_PCIDF_MSK 0x00000078 /* PCI division factor */
979 #define CPM_IMMR_OFFSET 0x101a8
982 #define FCC_PSMR_RMII ((uint)0x00020000) /* Use RMII interface */
1001 #define CMX1_CLK_MASK ((uint)0xff000000)
1006 #define CMX2_CLK_MASK ((uint)0x00ff0000)
1011 #define CMX3_CLK_MASK ((uint)0x0000ff00)
1021 #define PA1_COL 0x00000001U
1022 #define PA1_CRS 0x00000002U
1023 #define PA1_TXER 0x00000004U
1024 #define PA1_TXEN 0x00000008U
1025 #define PA1_RXDV 0x00000010U
1026 #define PA1_RXER 0x00000020U
1027 #define PA1_TXDAT 0x00003c00U
1028 #define PA1_RXDAT 0x0003c000U
1039 #define PB2_TXER 0x00000001U
1040 #define PB2_RXDV 0x00000002U
1041 #define PB2_TXEN 0x00000004U
1042 #define PB2_RXER 0x00000008U
1043 #define PB2_COL 0x00000010U
1044 #define PB2_CRS 0x00000020U
1045 #define PB2_TXDAT 0x000003c0U
1046 #define PB2_RXDAT 0x00003c00U
1057 #define PB3_RXDV 0x00004000U
1058 #define PB3_RXER 0x00008000U
1059 #define PB3_TXER 0x00010000U
1060 #define PB3_TXEN 0x00020000U
1061 #define PB3_COL 0x00040000U
1062 #define PB3_CRS 0x00080000U
1063 #define PB3_TXDAT 0x0f000000U
1064 #define PC3_TXDAT 0x00000010U
1065 #define PB3_RXDAT 0x00f00000U
1068 #define PB3_PSORB1 0
1075 #define FCC1_MEM_OFFSET FCC_MEM_OFFSET(0)
1080 #define MPC82XX_BCR_PLDP 0x00800000
1103 CPM_CLK_NONE = 0,
1138 #define CPM_PIN_INPUT 0
1140 #define CPM_PIN_PRIMARY 0