Lines Matching +full:cpm +full:- +full:command
1 /* SPDX-License-Identifier: GPL-2.0 */
7 * processor channels. Some CPM control and status is available
10 * CPM capabilities. I (or someone else) will add definitions as they
11 * are needed. -- Dan
13 * On the MBX board, EPPC-Bug loads CPM microcode into the first 512
24 #include <asm/cpm.h>
26 /* CPM Command register.
308 /* CPM Ethernet through SCCx.
331 uint sen_tbuf0data0; /* Save area 0 - current frame */
332 uint sen_tbuf0data1; /* Save area 1 - current frame */
343 uint sen_tbuf1data0; /* Save area 0 - current frame */
344 uint sen_tbuf1data1; /* Save area 1 - current frame */
448 /* CPM Transparent mode SCC.
494 unsigned long tm_cmd; /* RISC Timer Command Register */
498 /* Bits in RISC Timer Command Register */
499 #define TM_CMD_VALID 0x80000000 /* Valid - Enables the timer */
500 #define TM_CMD_RESTART 0x40000000 /* Restart - for automatic restart */
505 /* CPM interrupts. There are nearly 32 interrupts generated by CPM
507 * as a single interrupt. The CPM interrupt handler dispatches its
543 /* CPM interrupt configuration vector.
550 #define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */