Lines Matching +full:spe +full:- +full:pmu
1 /* SPDX-License-Identifier: GPL-2.0 */
6 * on-chip system devices (memory controller, IO controller, etc...)
19 #include <asm/cell-pmu.h>
43 u8 spe[8]; member
50 u32 spe; member
61 u8 pad_0x0010_0x00a8 [0x00a8 - 0x0010]; /* 0x0010 */
65 u8 pad_0x00b0_0x0100 [0x0100 - 0x00b0]; /* 0x00b0 */
73 u8 pad_0x0128_0x0400 [0x0400 - 0x0128]; /* 0x0128 */
83 u8 pad_0x0480_0x0800 [0x0800 - 0x0480]; /* 0x0480 */
111 u8 pad_0x0898_0x0c00 [0x0c00 - 0x0898]; /* 0x0898 */
122 u8 pad_0x0c28_0x0ca8 [0x0ca8 - 0x0c28]; /* 0x0c28 */
124 u8 pad_0x0cb0_0x1000 [0x1000 - 0x0cb0]; /* 0x0cb0 */
131 * PMU shadow registers
133 * Many of the registers in the performance monitoring unit are write-only,
137 * only takes effect if the PMU is enabled. Otherwise the value is stored in
138 * a hardware latch until the next time the PMU is enabled. So we save a copy
139 * of the counter values if we need to read them back while the PMU is
187 u8 pad_0x0000_0x0400[0x0400 - 0x0000]; /* 0x0000 */
204 u8 pad_0x0450_0x0500[0x0500 - 0x0450]; /* 0x0450 */
214 u8 pad_0x0530_0x1000[0x1000 - 0x0530]; /* 0x0530 */
222 u8 pad_0x0000_0x0040[0x0040 - 0x0000]; /* 0x0000 */
248 u8 pad_0x00a0_0x00f8[0x00f8 - 0x00a0]; /* 0x00a0 */
251 u8 pad_0x0100_0x01b8[0x01b8 - 0x0100]; /* 0x0100 */
262 u8 pad_0x01e0_0x0208[0x0208 - 0x01e0]; /* 0x01e0 */
277 u8 pad_0x0220_0x0230[0x0230 - 0x0220]; /* 0x0220 */
301 u8 pad_0x0240_0x1000[0x1000 - 0x0240]; /* 0x0240 */