Lines Matching +full:- +full:10
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
10 # Poly1305 - this version mainly using vector/VSX/Scalar
11 # - 26 bits limbs
12 # - Handle multiple 64 byte blcok.
17 # p = 2^130 - 5
25 # 07/22/21 - this revison based on the above sum of products. Setup r^4, r^3, r^2, r and s3, s2, …
56 #include <asm/asm-offsets.h>
57 #include <asm/asm-compat.h>
95 stdu 1,-752(1)
221 vmulouw 10, 5, 3
226 vaddudm 14, 14, 10
228 vmulouw 10, 5, 26
232 vaddudm 15, 15, 10
239 vmulouw 10, 5, 27
241 vaddudm 16, 16, 10
248 vmulouw 10, 5, 28
250 vaddudm 17, 17, 10
257 vmulouw 10, 5, 29
259 vaddudm 18, 18, 10
269 vmuleuw 10, 5, 3
274 vaddudm 14, 14, 10
280 vmuleuw 10, 5, 26
285 vaddudm 15, 15, 10
291 vmuleuw 10, 5, 27
296 vaddudm 16, 16, 10
302 vmuleuw 10, 5, 28
307 vaddudm 17, 17, 10
313 vmuleuw 10, 5, 29
318 vaddudm 18, 18, 10
376 vsld 10, 28, 13
380 vaddudm 1, 10, 28
392 vsld 10, 28, 13
396 vaddudm 1, 10, 28
412 vspltw 10, 26, 2
413 vmrgow 26, 10, 9
415 vspltw 10, 27, 2
416 vmrgow 27, 10, 9
418 vspltw 10, 28, 2
419 vmrgow 28, 10, 9
421 vspltw 10, 29, 2
422 vmrgow 29, 10, 9
424 vspltw 10, 30, 2
425 vmrgow 30, 10, 9
428 vsld 10, 28, 13
432 vaddudm 1, 10, 28
443 vsrd 10, 14, 31
449 vaddudm 15, 15, 10
455 vsld 10, 12, 9
460 vaddudm 4, 4, 10
461 vsrd 10, 4, 31
467 vaddudm 5, 5, 10
476 addis 10, 2, rmask@toc@ha
477 addi 10, 10, rmask@toc@l
479 ld 11, 0(10)
480 ld 12, 8(10)
484 addis 10, 2, cnum@toc@ha
485 addi 10, 10, cnum@toc@l
486 lvx 25, 0, 10 # v25 - mask
487 lvx 31, 14, 10 # v31 = 1a
488 lvx 19, 15, 10 # v19 = 1 << 24
489 lxv 24, 48(10) # vs24
490 lxv 25, 64(10) # vs25
495 ld 10, 32(3)
497 and. 10, 10, 12
504 insrdi 16, 10, 14, 38
506 extrdi 17, 10, 26, 24
508 extrdi 18, 10, 24, 0
544 ld 10, 8(3)
552 insrdi 16, 10, 14, 38
554 extrdi 17, 10, 26, 24
556 extrdi 18, 10, 24, 0
571 vsrd 10, 14, 31 # >> 26
572 vsrd 11, 10, 31 # 12 bits left
573 vand 10, 10, 25 # a1
585 vaddudm 21, 5, 10
598 vsrd 10, 14, 31 # >> 26
599 vsrd 11, 10, 31 # 12 bits left
600 vand 10, 10, 25 # a1
613 vmrgow 5, 10, 21
619 addi 5, 5, -64 # len -= 64
633 # h3 = (h1 + m3) * r^2, h4 = (h2 + m4) * r^2 --> (h0 + m1) r*4 + (h3 + m3) r^2, (h0 + m2) r^4 + (h…
635 # h5 = (h3 + m5) * r^2, h6 = (h4 + m6) * r^2 -->
636 # h7 = (h5 + m7) * r^2, h8 = (h6 + m8) * r^1 --> m5 * r^4 + m6 * r^3 + m7 * r^2 + m8 * r
645 vsrd 10, 14, 31
651 vaddudm 15, 15, 10
657 vsld 10, 12, 9
662 vaddudm 4, 4, 10
663 vsrd 10, 4, 31
669 vaddudm 5, 5, 10
692 vsrd 10, 17, 31 # >> 26
693 vsrd 11, 10, 31 # 12 bits left
696 vand 10, 10, 25 # a1
723 vmrgow 5, 10, 5
729 addi 5, 5, -64 # len -= 64
754 vaddudm 5, 15, 10
768 vsrd 10, 4, 31
774 vaddudm 5, 5, 10
780 vsld 10, 12, 9
785 vaddudm 4, 4, 10
786 vsrd 10, 4, 31
792 vaddudm 5, 5, 10
793 vsrd 10, 5, 31
795 vaddudm 6, 6, 10
844 addis 10, 2, rmask@toc@ha
845 addi 10, 10, rmask@toc@l
846 ld 11, 0(10)
847 ld 12, 8(10)
852 ld 10, 32(3)
854 and. 10, 10, 12 # cramp mask r1
856 srdi 21, 10, 2
857 add 19, 21, 10 # s1: r19 - (r1 >> 2) *5
862 mtvsrdd 32+1, 10, 9 # r1, r0
882 vmsumudm 10, 8, 2, 11 # d1 += h2 * s1
898 mfvsrld 28, 32+10
901 mfvsrd 21, 32+10 # h1.h
923 # - no highbit if final leftover block (highbit = 0)
931 stdu 1,-400(1)
1034 ld 10, 0(3)
1039 # h + 5 + (-p)
1040 mr 6, 10
1049 mr 10, 6
1056 addc 10, 10, 6
1060 std 10, 0(5)