Lines Matching +full:io +full:- +full:channel +full:- +full:ranges
1 // SPDX-License-Identifier: GPL-2.0-only
7 * xMon boot loader memory map which differs from U-Boot's.
10 /dts-v1/;
15 #address-cells = <1>;
16 #size-cells = <1>;
17 form-factor = "PMC/XMC";
18 boot-bank = <0x0>;
33 #address-cells = <1>;
34 #size-cells = <0>;
39 d-cache-line-size = <32>; // 32 bytes
40 i-cache-line-size = <32>; // 32 bytes
41 d-cache-size = <0x8000>; // L1, 32K
42 i-cache-size = <0x8000>; // L1, 32K
43 next-level-cache = <&L2>;
53 #address-cells = <1>;
54 #size-cells = <1>;
56 ranges = <0x0 0xef000000 0x100000>;
57 bus-frequency = <0>;
58 compatible = "fsl,mpc8548-immr", "simple-bus";
60 ecm-law@0 {
61 compatible = "fsl,ecm-law";
63 fsl,num-laws = <12>;
67 compatible = "fsl,mpc8548-ecm", "fsl,ecm";
70 interrupt-parent = <&mpic>;
73 memory-controller@2000 {
74 compatible = "fsl,mpc8548-memory-controller";
76 interrupt-parent = <&mpic>;
80 L2: l2-cache-controller@20000 {
81 compatible = "fsl,mpc8548-l2-cache-controller";
83 cache-line-size = <32>; // 32 bytes
84 cache-size = <0x80000>; // L2, 512K
85 interrupt-parent = <&mpic>;
89 /* On-card I2C */
91 #address-cells = <1>;
92 #size-cells = <0>;
93 cell-index = <0>;
94 compatible = "fsl-i2c";
97 interrupt-parent = <&mpic>;
102 * 0: BRD_CFG0 (1: P14 IO present)
104 * 2: BRD_CFG2 (1: XMC IO present)
114 #gpio-cells = <2>;
115 gpio-controller;
123 #gpio-cells = <2>;
124 gpio-controller;
145 /* Off-card I2C */
147 #address-cells = <1>;
148 #size-cells = <0>;
149 cell-index = <1>;
150 compatible = "fsl-i2c";
153 interrupt-parent = <&mpic>;
158 #address-cells = <1>;
159 #size-cells = <1>;
160 compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
162 ranges = <0x0 0x21100 0x200>;
163 cell-index = <0>;
164 dma-channel@0 {
165 compatible = "fsl,mpc8548-dma-channel",
166 "fsl,eloplus-dma-channel";
168 cell-index = <0>;
169 interrupt-parent = <&mpic>;
172 dma-channel@80 {
173 compatible = "fsl,mpc8548-dma-channel",
174 "fsl,eloplus-dma-channel";
176 cell-index = <1>;
177 interrupt-parent = <&mpic>;
180 dma-channel@100 {
181 compatible = "fsl,mpc8548-dma-channel",
182 "fsl,eloplus-dma-channel";
184 cell-index = <2>;
185 interrupt-parent = <&mpic>;
188 dma-channel@180 {
189 compatible = "fsl,mpc8548-dma-channel",
190 "fsl,eloplus-dma-channel";
192 cell-index = <3>;
193 interrupt-parent = <&mpic>;
200 #address-cells = <1>;
201 #size-cells = <1>;
202 cell-index = <0>;
207 ranges = <0x0 0x24000 0x1000>;
208 local-mac-address = [ 00 00 00 00 00 00 ];
210 interrupt-parent = <&mpic>;
211 tbi-handle = <&tbi0>;
212 phy-handle = <&phy0>;
215 #address-cells = <1>;
216 #size-cells = <0>;
217 compatible = "fsl,gianfar-mdio";
220 phy0: ethernet-phy@1 {
221 interrupt-parent = <&mpic>;
225 phy1: ethernet-phy@2 {
226 interrupt-parent = <&mpic>;
230 phy2: ethernet-phy@3 {
231 interrupt-parent = <&mpic>;
235 phy3: ethernet-phy@4 {
236 interrupt-parent = <&mpic>;
240 tbi0: tbi-phy@11 {
242 device_type = "tbi-phy";
249 #address-cells = <1>;
250 #size-cells = <1>;
251 cell-index = <1>;
256 ranges = <0x0 0x25000 0x1000>;
257 local-mac-address = [ 00 00 00 00 00 00 ];
259 interrupt-parent = <&mpic>;
260 tbi-handle = <&tbi1>;
261 phy-handle = <&phy1>;
264 #address-cells = <1>;
265 #size-cells = <0>;
266 compatible = "fsl,gianfar-tbi";
269 tbi1: tbi-phy@11 {
271 device_type = "tbi-phy";
278 #address-cells = <1>;
279 #size-cells = <1>;
280 cell-index = <2>;
285 ranges = <0x0 0x26000 0x1000>;
286 local-mac-address = [ 00 00 00 00 00 00 ];
288 interrupt-parent = <&mpic>;
289 tbi-handle = <&tbi2>;
290 phy-handle = <&phy2>;
293 #address-cells = <1>;
294 #size-cells = <0>;
295 compatible = "fsl,gianfar-tbi";
298 tbi2: tbi-phy@11 {
300 device_type = "tbi-phy";
307 #address-cells = <1>;
308 #size-cells = <1>;
309 cell-index = <3>;
314 ranges = <0x0 0x27000 0x1000>;
315 local-mac-address = [ 00 00 00 00 00 00 ];
317 interrupt-parent = <&mpic>;
318 tbi-handle = <&tbi3>;
319 phy-handle = <&phy3>;
322 #address-cells = <1>;
323 #size-cells = <0>;
324 compatible = "fsl,gianfar-tbi";
327 tbi3: tbi-phy@11 {
329 device_type = "tbi-phy";
335 cell-index = <0>;
339 clock-frequency = <0>;
340 current-speed = <9600>;
342 interrupt-parent = <&mpic>;
346 cell-index = <1>;
350 clock-frequency = <0>;
351 current-speed = <9600>;
353 interrupt-parent = <&mpic>;
356 global-utilities@e0000 { // global utilities reg
357 compatible = "fsl,mpc8548-guts";
359 fsl,has-rstcr;
363 interrupt-controller;
364 #address-cells = <0>;
365 #interrupt-cells = <2>;
367 compatible = "chrp,open-pic";
368 device_type = "open-pic";
373 compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus",
374 "simple-bus";
375 #address-cells = <2>;
376 #size-cells = <1>;
378 interrupt-parent = <&mpic>;
381 ranges = <
388 nor-boot@0,0 {
389 #address-cells = <1>;
390 #size-cells = <1>;
391 compatible = "cfi-flash";
393 bank-width = <2>;
413 nor-alternate@1,0 {
414 #address-cells = <1>;
415 #size-cells = <1>;
416 compatible = "cfi-flash";
418 bank-width = <2>;
431 #address-cells = <1>;
432 #size-cells = <1>;
433 compatible = "xes,address-ctl-nand";
435 cle-line = <0x8>; /* CLE tied to A3 */
436 ale-line = <0x10>; /* ALE tied to A4 */
447 #interrupt-cells = <1>;
448 #size-cells = <2>;
449 #address-cells = <3>;
450 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
453 clock-frequency = <33333333>;
454 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
455 interrupt-map = <
460 interrupt-parent = <&mpic>;
462 bus-range = <0 0>;
463 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
469 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
470 interrupt-map = <
477 interrupt-parent = <&mpic>;
479 bus-range = <0 0xff>;
480 ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x20000000
482 clock-frequency = <33333333>;
483 #interrupt-cells = <1>;
484 #size-cells = <2>;
485 #address-cells = <3>;
487 compatible = "fsl,mpc8548-pcie";
491 #size-cells = <2>;
492 #address-cells = <3>;
494 ranges = <0x02000000 0 0xc0000000 0x02000000 0
503 stdout-path = &serial0;